Lines Matching +full:hdmi +full:- +full:dp2
6 * Description header file of general definitions for OS and pre-OS video drivers
31 * If a change in VBIOS/Driver/Tool's interface is only needed for pre-SoC15 products, then the chan…
115 ATOM_SCALER_DISABLE =0, /*scaler bypass mode, auto-center & no replication*/
116 ATOM_SCALER_CENTER =1, //For Fudo, it's bypass and auto-center & auto replication
201 #define BIOS_VERSION_PREFIX "ATOMBIOSBK-AMD"
244 …tom_string_def atom_bios_string; //Signature to distinguish between Atombios and non-atombios,
603 uint32_t maco_pwrlimit_mw; // bomaco mode power limit in unit of m-watt
604 uint32_t usb_pwrlimit_mw; // power limit when USB is enable in unit of m-watt
655 eDP_TO_LVDS_RX_DISABLE = 0x00, // no eDP->LVDS translator chip
656 …eDP_TO_LVDS_COMMON_ID = 0x01, // common eDP->LVDS translator chip without A…
682 /* gpio_id pre-define id for multiple usage */
693 …/* ucGPIO=DRAM_SELF_REFRESH_GPIO_PIND uses for memory self refresh (ucGPIO=0, DRAM self-refresh; …
695 /* Thermal interrupt output->system thermal chip GPIO pin */
703 … included in the structure is calcualted by using the (whole structure size - the header size)/siz…
786 ATOM_ENCODER_CAP_RECORD_DP2 =0x10, // DP2 is supported by ASIC/board.
787 …ATOM_ENCODER_CAP_RECORD_UHBR10_EN =0x20, // DP2.0 UHBR10 settings is supported…
788 …ATOM_ENCODER_CAP_RECORD_UHBR13_5_EN =0x40, // DP2.0 UHBR13.5 settings is support…
789 …ATOM_ENCODER_CAP_RECORD_UHBR20_EN =0x80, // DP2.0 UHBR20 settings is supported…
790 ATOM_ENCODER_CAP_RECORD_USB_C_TYPE =0x100, // the DP connector is a USB-C type.
801 …ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY = 0x01, //a cap bit to indicate that this non-e…
815 uint8_t gpio_pinstate; // Pin state showing how to set-up the pin
963 … in the structure is calculated by using the (whole structure size - the header size- number_of_pa…
972 // (whole structure size - the header size- number_of_path)/size of atom_display_object_path
1113 …uint32_t max_mclk_chg_lat; // Worst case blackout duration for a memory clock frequency (p-state)…
1184 …// Worst case blackout duration for a memory clock frequency (p-state) change, units of 100s of ns…
1230 EXT_DISPLAY_PATH_CAPS__HDMI20_PARADE_PS175 = (0x03 << 2) //Parade DP->HDMI recoverter chip
1289 uint8_t encoder_mode; //atom_encode_mode_def, =2: DVI, =3: HDMI mode
1335 uint8_t encoder_mode; //atom_encode_mode_def, =2: DVI, =3: HDMI mode
1415 struct atom_hdmi_retimer_redriver_set dp2_retimer_set; //for DP2
1464 struct atom_hdmi_retimer_redriver_set dp2_retimer_set; //for DP2
1522 struct atom_hdmi_retimer_redriver_set dp2_retimer_set; //for DP2
1611 //memorytype DMI Type 17 offset 12h - Memory Type
1632 Ddr2FbdimmMemType, ///< Assign 20 to DDR2 FB-DIMM
2664 uint8_t LedPin3; // GPIO number for LedPin[3] - PCIE GEN Speed
2665 uint8_t LedPin4; // GPIO number for LedPin[4] - PMFW Error Status
2703 …uint8_t FchUsbPdSlaveAddr; //For requesting USB PD controller S-states via FCH I2C when enter…
3404 …VOLTAGE_OBJ_GPIO_LUT = 0, //VOLTAGE and GPIO Lookup table ->atom_gpio_voltage…
3405 …VOLTAGE_OBJ_VR_I2C_INIT_SEQ = 3, //VOLTAGE REGULATOR INIT sequece through I2C -> ato…
3406 …VOLTAGE_OBJ_PHASE_LUT = 4, //Set Vregulator Phase lookup table ->atom_gpio_vol…
3407 …VOLTAGE_OBJ_SVID2 = 7, //Indicate voltage control by SVID2 ->atom_svid2_vo…
3419 uint8_t i2c_flag; // Bit0: 0 - One byte data; 1 - Two byte data
3898 …uint8_t deep_color_ratio; // HDMI panel bit depth: enum atom_set_pixel_clock_v1_7_deepc…
3922 …PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_DIS = 0x00, //00 - DCCG_DEEP_COLOR_DTO_DISABLE: Disab…
3923 …PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_5_4 = 0x01, //01 - DCCG_DEEP_COLOR_DTO_5_4_RATIO: Set…
3924 …PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_3_2 = 0x02, //02 - DCCG_DEEP_COLOR_DTO_3_2_RATIO: Set…
3925 …PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_2_1 = 0x03, //03 - DCCG_DEEP_COLOR_DTO_2_1_RATIO: Set…
3966 …DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_DIS = 0x00, //00 - DCCG_DEEP_COLOR_DTO_DISABLE: Disab…
3967 …DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_5_4 = 0x01, //01 - DCCG_DEEP_COLOR_DTO_5_4_RATIO: Set…
3968 …DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_3_2 = 0x02, //02 - DCCG_DEEP_COLOR_DTO_3_2_RATIO: Set…
3969 …DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_2_1 = 0x03, //03 - DCCG_DEEP_COLOR_DTO_2_1_RATIO: Set…
4175 uint8_t digfe_sel; // DIG stream( front-end ) selection, bit0 means DIG0 FE is enable,
4215 …uint8_t dplaneset; // DP voltage swing and pre-emphasis value defined in DPCD DP_LANE_SET, "D…
4220 uint8_t digfe_sel; // DIG stream( front-end ) selection, bit0 means DIG0 FE is enable,