Lines Matching full:ppll
1820 // 0 means disable PPLL
1827 UCHAR ucCRTC; // Which CRTC uses this Ppll
1840 // 0 means disable PPLL
1847 UCHAR ucCRTC; // Which CRTC uses this Ppll
1887 … // 0 means disable PPLL. For VGA PPLL,make sure this value is not 0.
1900 … // bit[3]=0:use PPLL for dispclk source, =1: use engine clock for dispclock source
1917 // 0 means disable PPLL/DCPLL.
1925 UCHAR ucMiscInfo; // bit[0]= Force program PPLL
1928 // bit[4]= RefClock source for PPLL.
1951 … // 0 means disable PPLL/DCPLL. Expanded to 24 bits comparing to previous version.
1954 … // 0 means disable PPLL/DCPLL. Expanded to 24 bits comparing to previous version.
1973 UCHAR ucMiscInfo; // bit[0]= Force program PPLL
1976 // bit[4]= RefClock source for PPLL.
2025 // bit[5:4]= RefClock source for PPLL.
2079 …UCHAR ucDCEClkFlag; // Bit [1:0] = PPLL ref clock source ( when ucD…
2155 …ULONG ulDispPllFreq; // return display PPLL freq which is used to generate the pix…
2156 … // if it is none-zero, it is used to be calculated the other ppll parameter fb_divide…
2157 … // if it is none-zero, it is used to be calculated the other ppll parameter fb_divider
2296 //This new structure is based on ENABLE_LVDS_SS_PARAMETERS but expands to SS on PPLL, so other devi…
3127 … //In 10Khz unit, if it is 0, In DP Mode Uniphy Input clock from internal PPLL, otherwise Input cl…
3175 … //In 10Khz unit, if it is 0, In DP Mode Uniphy Input clock from internal PPLL, otherwise Input cl…
4135 … Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Bit2=1: PCIE REFCLK SS =0 iternal PPLL SS Others:TBD