Lines Matching +full:1 +full:khz
58 #define ATOM_DAC_B 1
62 #define ATOM_CRTC2 1
74 #define ATOM_DIGB 1
77 #define ATOM_PPLL2 1
102 #define ENCODER_REFCLK_SRC_P2PLL 1
108 #define ATOM_SCALER_CENTER 1 //For Fudo, it's bypass and auto-center & auto replication
113 #define ATOM_ENABLE 1
123 #define ATOM_BLANKING 1
128 #define ATOM_CRT2 1
130 #define ATOM_TV_NTSC 1
140 #define ATOM_DAC1_PS2 1
151 #define ATOM_PM_STANDBY 1
156 // Bit0:{=0:single, =1:dual},
157 // Bit1 {=0:666RGB, =1:888RGB},
159 // Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888}
189 #define HW_ASSISTED_I2C_STATUS_SUCCESS 1
191 #pragma pack(1) // BIOS data must use byte alignment
319 …USHORT SetDCEClock; //Atomic Table, start from DCE11.1, shared by driv…
392 USHORT UpdatedByUtility:1; //[15]=Table updated by utility flag
398 USHORT UpdatedByUtility:1; //[15]=Table updated by utility flag
417 #define COMPUTE_MEMORY_PLL_PARAM 1
427 …ULONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYT…
433 …ULONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYT…
441 UCHAR ucAction; //0:reserved //1:Memory //2:Engine
461 …pplicable to both memory and engine clock change,when set, it means this is 1st time to change clo…
468 …pplicable to both memory and engine clock change,when set, it means this is 1st time to change clo…
478 …ULONG ulComputeClockFlag:8; // =1: COMPUTE_MEMORY_PLL_PARAM, =2: COMPUTE_ENGINE_PL…
479 ULONG ulClockFreq:24; // in unit of 10kHz
481 ULONG ulClockFreq:24; // in unit of 10kHz
482 …ULONG ulComputeClockFlag:8; // =1: COMPUTE_MEMORY_PLL_PARAM, =2: COMPUTE_ENGINE_PL…
507 #define ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN 1
538 …UCHAR ucInputFlag; //Input Flags. ucInputFlag[0] - Strobe(1)/Performance(0)…
586 UCHAR ucSclkVcoMode; //0: 4G~8Ghz, 1:3G~6Ghz,3: 2G~4Ghz, 2:Reserved
598 #define ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN 1 // 1-StrobeMode, 0-PerformanceMode
611 …UCHAR ucInputFlag; //Input : ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN: 1-Stro…
659 //Input parameter of DynamicMemorySettingsTable ver2.1 and above
671 #define DYNAMIC_MC_DPM_SETTING_MEDIUM_DPM_STATE 1
687 ULONG ulTargetEngineClock; //In 10Khz unit
692 ULONG ulTargetEngineClock; //In 10Khz unit
698 ULONG ulTargetEngineClock; //In 10Khz unit
708 ULONG ulTargetMemoryClock; //In 10Khz unit
713 ULONG ulTargetMemoryClock; //In 10Khz unit
722 ULONG ulDefaultEngineClock; //In 10Khz unit
723 ULONG ulDefaultMemoryClock; //In 10Khz unit
740 ASIC_INIT_CLOCK_PARAMETERS asSclkClock; //In 10Khz unit
741 ASIC_INIT_CLOCK_PARAMETERS asMemClock; //In 10Khz unit
812 USHORT usPixelClock; // in 10KHz; for bios convenient
813 …tion of ATOM_DACx_xxx, For DEC3.0, bit 7 used as internal flag to indicate DAC2 (==1) or DAC1 (==0)
815 // 1: setup and turn on encoder
828 USHORT usPixelClock; // in 10KHz; for bios convenient
832 // =1: PHY linkB if bfLanes<3
836 // =1: LVTMA
838 // =1: turn on encoder
841 // =1: LVDS encoder
873 #define ATOM_ENCODER_MODE_LVDS 1
890 UCHAR ucTransmitterSel:2; // =0: UniphyAB, =1: UniphyCD =2: UniphyEF
891 UCHAR ucLinkSel:1; // =0: linkA/C/E =1: linkB/D/F
892 UCHAR ucReserved:1;
893 UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz
895 UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz
896 UCHAR ucReserved:1;
897 UCHAR ucLinkSel:1; // =0: linkA/C/E =1: linkB/D/F
898 UCHAR ucTransmitterSel:2; // =0: UniphyAB, =1: UniphyCD =2: UniphyEF
906 USHORT usPixelClock; // in 10KHz; for bios convenient
911 // =1: LVDS encoder
956 //ucTableFormatRevision=1
962 UCHAR ucReserved1:1;
963 …UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as D…
965 UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz
967 UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz
969 …UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as D…
970 UCHAR ucReserved1:1;
987 USHORT usPixelClock; // in 10KHz; for bios convenient
993 // =1: LVDS encoder
1008 //ucTableFormatRevision=1
1015 UCHAR ucReserved1:1;
1016 …UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as D…
1018 …UCHAR ucDPLinkRate:2; // =0: 1.62Ghz, =1: 2.7Ghz, 2=5.4Ghz <= Changed comparing to prev…
1020 …UCHAR ucDPLinkRate:2; // =0: 1.62Ghz, =1: 2.7Ghz, 2=5.4Ghz <= Changed comparing to prev…
1022 …UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as D…
1023 UCHAR ucReserved1:1;
1043 USHORT usPixelClock; // in 10KHz; for bios convenient
1052 // =1: LVDS encoder
1064 …UCHAR ucHPD_ID; // HPD ID (1-6). =0 means to skip HDP programming. New comparing to prev…
1087 ULONG ulPixelClock; // Pixel Clock in 10Khz
1099 ULONG ulSymClock; // Symbol Clock in 10Khz
1158 USHORT usPixelClock; // in 10KHz; for bios convenient
1164 // =1: 8 lane Link ( Dual Links TMDS )
1165 // [1]=0: InCoherent mode
1166 // =1: Coherent Mode
1169 // =1: PHY linkB if bfLanes<3
1173 // =1: lane 4~7
1177 // =1: turn on encoder
1213 #define ATOM_TRANSMITTER_ACTION_ENABLE 1
1231 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
1232 // =1 Dig Transmitter 2 ( Uniphy CD )
1234 UCHAR ucReserved:1;
1235 UCHAR fDPConnector:1; //bit4=0: DP connector =1: None DP connector
1236 …UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA( DIG inst0 ). =1: Data/…
1237 …UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when…
1238 …// =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means ma…
1240 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode )
1241 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector
1243 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector
1244 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode )
1245 …UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when…
1246 …// =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means ma…
1247 …UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA( DIG inst0 ). =1: Data/…
1248 UCHAR fDPConnector:1; //bit4=0: DP connector =1: None DP connector
1249 UCHAR ucReserved:1;
1250 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
1251 // =1 Dig Transmitter 2 ( Uniphy CD )
1286 USHORT usPixelClock; // in 10KHz; for bios convenient
1298 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
1299 // =1 Dig Transmitter 2 ( Uniphy CD )
1301 UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, EXT_CLK=2
1302 …UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path …
1303 …UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when…
1304 …// =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means ma…
1305 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode )
1306 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector
1308 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector
1309 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode )
1310 …UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when…
1311 …// =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means ma…
1312 …UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path …
1313 UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, EXT_CLK=2
1314 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
1315 // =1 Dig Transmitter 2 ( Uniphy CD )
1325 USHORT usPixelClock; // in 10KHz; for bios convenient
1368 // ucTableFormatRevision=1
1394 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
1395 // =1 Dig Transmitter 2 ( Uniphy CD )
1397 UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, DCPLL=2, EXT_CLK=3 <= New
1398 …UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path …
1399 …UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when…
1400 …// =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means ma…
1401 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode )
1402 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector
1404 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector
1405 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode )
1406 …UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when…
1407 …// =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means ma…
1408 …UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path …
1409 UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, DCPLL=2, EXT_CLK=3 <= New
1410 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
1411 // =1 Dig Transmitter 2 ( Uniphy CD )
1420 USHORT usPixelClock; // in 10KHz; for bios convenient
1463 UCHAR ucReservd1:1;
1466 UCHAR ucCoherentMode:1;
1467 UCHAR ucReserved:1;
1469 UCHAR ucReserved:1;
1470 UCHAR ucCoherentMode:1;
1473 UCHAR ucReservd1:1;
1479 …USHORT usSymClock; // Encoder Clock in 10kHz,(DP mode)= linkclock/10, (TMDS/LVDS/HDMI…
1480 …UCHAR ucPhyId; // 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4= UNIPHYE 5=UNIP…
1482 UCHAR ucLaneNum; // indicate lane number 1-8
1497 #define ATOM_PHY_ID_UNIPHYB 1
1515 #define ATOM_TRANSMITTER_DIGMODE_V5_LVDS 1
1561 UCHAR ucPhyId; // 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4= UNIPHYE 5=UNIPHYF
1569 ULONG ulSymClock; // Symbol Clock in 10Khz
1570 UCHAR ucHPDSel; // =1: HPD1, =2: HPD2, .... =6: HPD6, =0: HPD is not assigned
1606 // ucTableFormatRevision=1
1613 USHORT usPixelClock; // pixel clock in 10Khz, valid when ucAction=SETUP/ENABLE_OUTPUT
1794 //#define ATOM_ENCODER_MODE_LVDS 1
1816 //Major revision=1., Minor revision=1
1819 …USHORT usPixelClock; // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_D…
1831 //Major revision=1., Minor revision=2, add ucMiscIfno
1839 …USHORT usPixelClock; // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_D…
1851 //Major revision=1., Minor revision=3, structure/definition change
1886 …USHORT usPixelClock; // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_D…
1899 …UCHAR ucMiscInfo; // bit[0]=Force program, bit[1]= set pclk for VGA, b[2]= CRTC …
1900 … // bit[3]=0:use PPLL for dispclk source, =1: use engine clock for dispclock source
1901 …// bit[4]=0:use XTALIN as the source of reference divider,=1 use the pre-defined clock as the sour…
1926 // bit[1]= when VGA timing is used.
1927 // bit[3:2]= HDMI panel bit depth: =0: 24bpp =1:30bpp, =2:32bpp
1930 // =1: other external clock source, which is pre-defined
1933 …ULONG ulFbDivDecFrac; // 20 bit feedback divider decimal fraction part, range from 1~999999 (…
1974 // bit[1]= when VGA timing is used.
1975 // bit[3:2]= HDMI panel bit depth: =0: 24bpp =1:30bpp, =2:32bpp
1978 // =1: other external clock source, which is pre-defined
1981 …ULONG ulFbDivDecFrac; // 20 bit feedback divider decimal fraction part, range from 1~999999 (…
1990 …MI_36BPP_V6 0x08 //for V6, the correct definition for 36bpp should be 2 for 36bpp(2:1)
1992 …MI_30BPP_V6 0x04 //for V6, the correct definition for 30bpp should be 1 for 36bpp(5:4)
2006 …UCHAR ucRefDivSrc; // =1: reference clock source from XTALIN, =0: source from PCI…
2024 …// bit[1]= Force program PHY PLL only ( internally used by VBIOS only in DP case which PHYPLL is p…
2027 // =1: pcie
2030 UCHAR ucDeepColorRatio; // HDMI panel bit depth: =0: 24bpp =1:30bpp, =2:36bpp
2049 …PCOLOR_RATIO_2_1 0x03 //03 - DCCG_DEEP_COLOR_DTO_2_1_RATIO: Set Deep Color DTO to 2:1
2051 // SetDCEClockTable input parameter for DCE11.1
2054 …eq; // target DISPCLK frquency in unit of 10kHz, return real DISPCLK frequency. when ucFlag[…
2055 UCHAR ucFlag; // bit0=1: DPREFCLK bypass DFS bit0=0: DPREFCLK not bypass DFS
2056 UCHAR ucCrtc; // use when enable DCCG pixel clock ucFlag[1]=1
2057 UCHAR ucPpllId; // use when enable DCCG pixel clock ucFlag[1]=1
2058 UCHAR ucDeepColorRatio; // use when enable DCCG pixel clock ucFlag[1]=1
2076 …ULONG ulDCEClkFreq; // target DCE frequency in unit of 10KHZ, retur…
2077 UCHAR ucDCEClkType; // =0: DISPCLK =1: DPREFCLK =2: PIXCLK
2079 …UCHAR ucDCEClkFlag; // Bit [1:0] = PPLL ref clock source ( when ucD…
2080 …UCHAR ucCRTC; // ucDisp Pipe Id, ATOM_CRTC0/1/2/..., use only…
2085 #define DCE_CLOCK_TYPE_DPREFCLK 1
2100 …DEEPCOLOR_RATIO_2_1 0x03 //03 - DCCG_DEEP_COLOR_DTO_2_1_RATIO: Set Deep Color DTO to 2:1
2186 ULONG ulReturnMemoryClock; // current memory speed in 10KHz unit
2195 ULONG ulReturnEngineClock; // current engine speed in 10KHz unit
2209 … //WHen use input: lower byte as 'byte to read':currently limited to 128byte or 1byte
2217 #define ATOM_WRITE_I2C_FORMAT_PSOFFSET_PSTWODATABYTES 1
2227 //1bytePS+offsetPS
2233 UCHAR ucStatus; //Status byte 1=success, 2=failure, Also is used as PS data2
2256 UCHAR ucPowerConnectorStatus; //Used for return value 0: detected, 1:not detected
2263 UCHAR ucPowerConnectorStatus; //Used for return value 0: detected, 1:not detected
2278 …UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int.…
2284 //ucTableFormatRevision=1,ucTableContentRevision=2
2288 …UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int.…
2300 …UCHAR ucSpreadSpectrumType; // Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int…
2311 UCHAR ucSpreadSpectrumType; // Bit[0]: 0-Down Spread,1-Center Spread.
2312 // Bit[1]: 1-Ext. 0-Int.
2313 // Bit[3:2]: =0 P1PLL =1 P2PLL =2 DCPLL
2336 UCHAR ucSpreadSpectrumType; // Bit[0]: 0-Down Spread,1-Center Spread.
2337 // Bit[1]: 1-Ext. 0-Int.
2338 // Bit[3:2]: =0 P1PLL =1 P2PLL =2 DCPLL
2376 ULONG ulTargetMemoryClock; //In 10Khz unit
2389 #define ENTER_DRAM_SELFREFRESH_MODE 1
2402 USHORT usPixelClock; // in 10KHz; for bios convenient
2404 // =1: Enable dual link
2406 // =1: 888RGB
2408 // 1: setup and turn on encoder
2419 //ucTableFormatRevision=1,ucTableContentRevision=2
2422 USHORT usPixelClock; // in 10KHz; for bios convenient
2425 // 1: setup and turn on encoder
2427 // =1: Enable truncate
2429 // =1: 888RGB
2431 // =1: Enable spatial dithering
2433 // =1: 888RGB
2435 // =1: Enable temporal dithering
2437 // =1: 888RGB
2439 // =1: Gray level 4
2441 // =1: 25FRC_SEL pattern F
2443 // =1: 50FRC_SEL pattern B
2447 // =1: 75FRC_SEL pattern F
2474 …AR ucMisc; // Bit0=0:Enable Single link;=1:Enable Dual link;Bit1 {=0:666RGB, =1:88…
2500 //ucTableFormatRevision=1,ucTableContentRevision=3
2530 //ucTableFormatRevision=1
2531 //ucTableContentRevision=3 structure is not changed but usMisc add bit 1 as another input for
2533 // =1: coherent mode
2557 #define PANEL_ENCODER_ACTION_COHERENTSEQ (ATOM_ENABLE+1)
2581 #define SET_VOLTAGE_TYPE_ASIC_VDDC 1
2616 …USHORT usVoltageLevel; // real voltage level in unit of mv or Voltage Phase (0, 1, …
2620 #define VOLTAGE_TYPE_VDDC 1
2672 … // Input: real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. ) or Leakage …
2691 // GetVoltageInfo v1.1 ucVoltageMode
2711 … // Input: real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. ) or Leakage …
2733 … // Input: real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. ) or Leakage …
2765 USHORT usPixelClock; // in 10KHz; for bios convenient
2768 // 1: setup and turn on encoder
2860 …UCHAR ucMiscInfo1; // Tuner voltage (1:0) HW teletext support (3:2) FM aud…
2861 …UCHAR ucMiscInfo2; // I2S input config (0) I2S output config (1) I2S Audio…
2864 …UCHAR ucVideoInput0Info;// Video Input 0 Type (1:0) F/B setting (2) physical co…
2865 …UCHAR ucVideoInput1Info;// Video Input 1 Type (1:0) F/B setting (2) physical co…
2866 …UCHAR ucVideoInput2Info;// Video Input 2 Type (1:0) F/B setting (2) physical co…
2867 …UCHAR ucVideoInput3Info;// Video Input 3 Type (1:0) F/B setting (2) physical co…
2868 …UCHAR ucVideoInput4Info;// Video Input 4 Type (1:0) F/B setting (2) physical co…
2877 // Bit 0 = 0: Bios image is not Posted, =1:Bios image is Posted;
2878 // Bit 1 = 0: Dual CRTC is not supported, =1: Dual CRTC is supported;
2879 // Bit 2 = 0: Extended Desktop is not supported, =1: Extended Desktop is supported;
2884 #define ATOM_BIOS_INFO_MEMORY_CLOCK_SS_SUPPORT 0x0008 // (valid from v1.1 ~v1.4):=1: memc…
2885 #define ATOM_BIOS_INFO_ENGINE_CLOCK_SS_SUPPORT 0x0010 // (valid from v1.1 ~v1.4):=1: engc…
2893 #define ATOM_BIOS_INFO_MEMORY_CLOCK_EXT_SS_SUPPORT 0x0008 // (valid from v2.1 ): =1: memclk s…
2894 #define ATOM_BIOS_INFO_ENGINE_CLOCK_EXT_SS_SUPPORT 0x0010 // (valid from v2.1 ): =1: engclk s…
2903 USHORT Reserved:1;
2904 USHORT SCL2Redefined:1;
2905 USHORT PostWithoutModeSet:1;
2907 USHORT HyperMemory_Support:1;
2908 USHORT PPMode_Assigned:1;
2909 USHORT WMI_SUPPORT:1;
2910 USHORT GPUControlsBL:1;
2911 USHORT EngineClockSS_Support:1;
2912 USHORT MemoryClockSS_Support:1;
2913 USHORT ExtendedDesktopSupport:1;
2914 USHORT DualCRTC_Support:1;
2915 USHORT FirmwarePosted:1;
2917 USHORT FirmwarePosted:1;
2918 USHORT DualCRTC_Support:1;
2919 USHORT ExtendedDesktopSupport:1;
2920 USHORT MemoryClockSS_Support:1;
2921 USHORT EngineClockSS_Support:1;
2922 USHORT GPUControlsBL:1;
2923 USHORT WMI_SUPPORT:1;
2924 USHORT PPMode_Assigned:1;
2925 USHORT HyperMemory_Support:1;
2927 USHORT PostWithoutModeSet:1;
2928 USHORT SCL2Redefined:1;
2929 USHORT Reserved:1;
2952 ULONG ulDefaultEngineClock; //In 10Khz unit
2953 ULONG ulDefaultMemoryClock; //In 10Khz unit
2954 ULONG ulDriverTargetEngineClock; //In 10Khz unit
2955 ULONG ulDriverTargetMemoryClock; //In 10Khz unit
2956 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit
2957 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit
2958 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
2959 ULONG ulASICMaxEngineClock; //In 10Khz unit
2960 ULONG ulASICMaxMemoryClock; //In 10Khz unit
2964 USHORT usMinEngineClockPLL_Input; //In 10Khz unit
2965 USHORT usMaxEngineClockPLL_Input; //In 10Khz unit
2966 USHORT usMinEngineClockPLL_Output; //In 10Khz unit
2967 USHORT usMinMemoryClockPLL_Input; //In 10Khz unit
2968 USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit
2969 USHORT usMinMemoryClockPLL_Output; //In 10Khz unit
2970 USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk
2971 USHORT usMinPixelClockPLL_Input; //In 10Khz unit
2972 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit
2973 …USHORT usMinPixelClockPLL_Output; //In 10Khz unit, the definitions above…
2975 USHORT usReferenceClock; //In 10Khz unit
2976 … usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit
2986 ULONG ulDefaultEngineClock; //In 10Khz unit
2987 ULONG ulDefaultMemoryClock; //In 10Khz unit
2988 ULONG ulDriverTargetEngineClock; //In 10Khz unit
2989 ULONG ulDriverTargetMemoryClock; //In 10Khz unit
2990 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit
2991 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit
2992 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
2993 ULONG ulASICMaxEngineClock; //In 10Khz unit
2994 ULONG ulASICMaxMemoryClock; //In 10Khz unit
2999 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit
3000 USHORT usMinEngineClockPLL_Input; //In 10Khz unit
3001 USHORT usMaxEngineClockPLL_Input; //In 10Khz unit
3002 USHORT usMinEngineClockPLL_Output; //In 10Khz unit
3003 USHORT usMinMemoryClockPLL_Input; //In 10Khz unit
3004 USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit
3005 USHORT usMinMemoryClockPLL_Output; //In 10Khz unit
3006 USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk
3007 USHORT usMinPixelClockPLL_Input; //In 10Khz unit
3008 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit
3009 …USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMin…
3011 USHORT usReferenceClock; //In 10Khz unit
3012 … usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit
3022 ULONG ulDefaultEngineClock; //In 10Khz unit
3023 ULONG ulDefaultMemoryClock; //In 10Khz unit
3024 ULONG ulDriverTargetEngineClock; //In 10Khz unit
3025 ULONG ulDriverTargetMemoryClock; //In 10Khz unit
3026 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit
3027 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit
3028 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
3029 ULONG ulASICMaxEngineClock; //In 10Khz unit
3030 ULONG ulASICMaxMemoryClock; //In 10Khz unit
3035 ULONG ul3DAccelerationEngineClock;//In 10Khz unit
3036 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit
3037 USHORT usMinEngineClockPLL_Input; //In 10Khz unit
3038 USHORT usMaxEngineClockPLL_Input; //In 10Khz unit
3039 USHORT usMinEngineClockPLL_Output; //In 10Khz unit
3040 USHORT usMinMemoryClockPLL_Input; //In 10Khz unit
3041 USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit
3042 USHORT usMinMemoryClockPLL_Output; //In 10Khz unit
3043 USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk
3044 USHORT usMinPixelClockPLL_Input; //In 10Khz unit
3045 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit
3046 …USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMin…
3048 USHORT usReferenceClock; //In 10Khz unit
3049 … usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit
3059 ULONG ulDefaultEngineClock; //In 10Khz unit
3060 ULONG ulDefaultMemoryClock; //In 10Khz unit
3061 ULONG ulDriverTargetEngineClock; //In 10Khz unit
3062 ULONG ulDriverTargetMemoryClock; //In 10Khz unit
3063 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit
3064 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit
3065 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
3066 ULONG ulASICMaxEngineClock; //In 10Khz unit
3067 ULONG ulASICMaxMemoryClock; //In 10Khz unit
3073 ULONG ul3DAccelerationEngineClock;//In 10Khz unit
3074 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit
3075 USHORT usMinEngineClockPLL_Input; //In 10Khz unit
3076 USHORT usMaxEngineClockPLL_Input; //In 10Khz unit
3077 USHORT usMinEngineClockPLL_Output; //In 10Khz unit
3078 USHORT usMinMemoryClockPLL_Input; //In 10Khz unit
3079 USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit
3080 USHORT usMinMemoryClockPLL_Output; //In 10Khz unit
3081 USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk
3082 USHORT usMinPixelClockPLL_Input; //In 10Khz unit
3083 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit
3084 …USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMin…
3086 USHORT usReferenceClock; //In 10Khz unit
3087 … usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit
3098 ULONG ulDefaultEngineClock; //In 10Khz unit
3099 ULONG ulDefaultMemoryClock; //In 10Khz unit
3102 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit
3103 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit
3104 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
3106 ULONG ulDefaultDispEngineClkFreq; //In 10Khz unit
3113 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit
3114 USHORT usMinEngineClockPLL_Input; //In 10Khz unit
3115 USHORT usMaxEngineClockPLL_Input; //In 10Khz unit
3116 USHORT usMinEngineClockPLL_Output; //In 10Khz unit
3117 USHORT usMinMemoryClockPLL_Input; //In 10Khz unit
3118 USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit
3119 USHORT usMinMemoryClockPLL_Output; //In 10Khz unit
3120 USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk
3121 USHORT usMinPixelClockPLL_Input; //In 10Khz unit
3122 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit
3123 …USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMin…
3125 USHORT usCoreReferenceClock; //In 10Khz unit
3126 USHORT usMemoryReferenceClock; //In 10Khz unit
3127 …USHORT usUniphyDPModeExtClkFreq; //In 10Khz unit, if it is 0, In DP Mod…
3139 UCHAR ucEMBEDDED_CAP:2; // Bit[1:0] Embedded feature level
3148 ULONG ulDefaultEngineClock; //In 10Khz unit
3149 ULONG ulDefaultMemoryClock; //In 10Khz unit
3150 ULONG ulSPLL_OutputFreq; //In 10Khz unit
3151 ULONG ulGPUPLL_OutputFreq; //In 10Khz unit
3152 … ulReserved1; //Was ulMaxEngineClockPLL_Output; //In 10Khz unit*
3153 … ulReserved2; //Was ulMaxMemoryClockPLL_Output; //In 10Khz unit*
3154 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
3156 …ULONG ulDefaultDispEngineClkFreq; //In 10Khz unit. This is the frequency…
3163 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit
3168 …USHORT usReserved11; //Was usMaxPixelClock; //In 10Khz uni…
3169 USHORT usMinPixelClockPLL_Input; //In 10Khz unit
3170 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit
3173 USHORT usCoreReferenceClock; //In 10Khz unit
3174 USHORT usMemoryReferenceClock; //In 10Khz unit
3175 …USHORT usUniphyDPModeExtClkFreq; //In 10Khz unit, if it is 0, In DP Mod…
3177 …UCHAR ucCoolingSolution_ID; //0: Air cooling; 1: Liquid cooling ..…
3178 … // Bit[7:4]ucBRANDING_ID: Branding ID, Bit[3:2]ucReserved: Reserved, Bit[1:0]ucEMBEDDED_CAP: Em…
3203 ULONG ulBootUpEngineClock; //in 10kHz unit
3204 ULONG ulBootUpMemoryClock; //in 10kHz unit
3205 ULONG ulMaxSystemMemoryClock; //in 10kHz unit
3206 ULONG ulMinSystemMemoryClock; //in 10kHz unit
3215 … usCapabilityFlag; //Bit0=1 indicates the fake HDMI support,Bit1=0/1 …
3216 … //Bit[3:2]== 0:No PCIE card, 1:AC card, 2:SDVO card
3217 //Bit[4]==1: P/2 mode, ==0: P/1 mode
3224 …UCHAR ucMemoryType; //[7:4]=1:DDR1;=2:DDR2;=3:DDR3.[…
3252 …duty is 100%. high 8 bits of the value.If the PWM has an inverter,set bit [7]==1,otherwise set it 0
3275 ULONG ulBootUpEngineClock; //in 10kHz unit
3277 ULONG ulBootUpUMAClock; //in 10kHz unit
3278 ULONG ulBootUpSidePortClock; //in 10kHz unit
3279 ULONG ulMinSidePortClock; //in 10kHz unit
3286 …UCHAR ucMemoryType; //[3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is rese…
3296 ULONG ulHTLinkFreq; //in 10Khz
3303 ULONG ulHighVoltageHTLinkFreq; // in 10Khz
3304 ULONG ulLowVoltageHTLinkFreq; // in 10Khz
3315 ulBootUpEngineClock: Boot-up Engine Clock in 10Khz;
3316 ulBootUpUMAClock: Boot-up UMA Clock in 10Khz; it must be 0x0 when UMA is not present
3317 ulBootUpSidePortClock: Boot-up SidePort Clock in 10Khz; it must be 0x0 when SidePort Memory is not …
3320 Bit[0]=1: PowerExpress mode =0 Non-PowerExpress mode;
3321 Bit[1]=1: system boots up at AMD overdrived state or user customized mode. In this case, driver wi…
3323 Bit[2]=1: PWM method is used on NB voltage control. =0: GPIO method is used.
3324 Bit[3]=1: Only one power state(Performance) will be supported.
3326 Bit[4]=1: CLMC is supported and enabled on current system.
3328 Bit[5]=1: Enable CDLW for all driver control power states. Max HT width is from SBIOS, while Min HT…
3330 Bit[6]=1: High Voltage requested for all power states. In this case, voltage will be forced at 1.1v…
3332 Bit[7]=1: Enable CLMC as hybrid Mode. CDLD and CILR will be disabled in this case and we're using l…
3334 Bit[8]=1: CDLF is supported and enabled on current system.
3336 Bit[9]=1: DLL Shut Down feature is enabled on current system.
3341 ulOtherDisplayMisc: [15:8]- Bootup LCD Expansion selection; 0-center, 1-full panel size expansion;
3345 …fig of the DDI slot/connector on chassis (bit 0=1 lane 3:0; bit 1=1 lane 7:4; bit 2=1 lane 11:8; b…
3346 …me DDI slot/connector on docking station (bit 4=1 lane 3:0; bit 5=1 lane 7:4; bit 6=1 lane 11:8; b…
3370 ulCPUCapInfo: [7:0]=1:Griffin;[7:0]=2:Greyhound;[7:0]=3:K8, [7:0]=4:Pharaoh, other bits rese…
3377 …sMaxNBVoltage & usMinNBVoltage have a valid value ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE=1
3383 ulHTLinkFreq: Bootup HT link Frequency in 10Khz.
3411 #define INTEGRATED_SYSTEM_INFO__AMD_CPU__GRIFFIN 1
3449 ULONG ulBootUpEngineClock; //in 10kHz unit
3450 …ULONG ulDentistVCOFreq; //Dentist VCO clock in 10kHz unit, the sourc…
3451 …ULONG ulLClockFreq; //GPU Lclk freq in 10kHz unit, have relation…
3452 ULONG ulBootUpUMAClock; //in 10kHz unit
3470 …UCHAR ucMemoryType; //[3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is rese…
3535 #define ATOM_DIGITAL_ENCODER 1
3563 #define ATOM_MAX_SUPPORTED_DEVICE_INFO (ATOM_DEVICE_DFP3_INDEX+1)
3565 #define ATOM_MAX_SUPPORTED_DEVICE_INFO_3 (ATOM_DEVICE_DFP5_INDEX + 1 )
3567 #define ATOM_MAX_SUPPORTED_DEVICE (ATOM_DEVICE_RESERVEDF_INDEX+1)
3630 // Bits0 = 0 - no CRT1 support= 1- CRT1 is supported
3631 // Bit 1 = 0 - no LCD1 support= 1- LCD1 is supported
3632 // Bit 2 = 0 - no TV1 support= 1- TV1 is supported
3633 // Bit 3 = 0 - no DFP1 support= 1- DFP1 is supported
3634 // Bit 4 = 0 - no CRT2 support= 1- CRT2 is supported
3635 // Bit 5 = 0 - no LCD2 support= 1- LCD2 is supported
3636 // Bit 6 = 0 - no DFP6 support= 1- DFP6 is supported
3637 // Bit 7 = 0 - no DFP2 support= 1- DFP2 is supported
3638 // Bit 8 = 0 - no CV support= 1- CV is supported
3639 // Bit 9 = 0 - no DFP3 support= 1- DFP3 is supported
3640 // Bit 10= 0 - no DFP4 support= 1- DFP4 is supported
3641 // Bit 11= 0 - no DFP5 support= 1- DFP5 is supported
3651 // [7] - HW_Cap = 1, [6:0]=HW assisted I2C ID(HW line selection)
3653 // [6-4] - HW_ENGINE_ID = 1, HW engine for NON multimedia use
3661 UCHAR bfHW_Capable:1;
3667 UCHAR bfHW_Capable:1;
3721 USHORT RGB888:1;
3722 USHORT DoubleClock:1;
3723 USHORT Interlace:1;
3724 USHORT CompositeSync:1;
3725 USHORT V_ReplicationBy2:1;
3726 USHORT H_ReplicationBy2:1;
3727 USHORT VerticalCutOff:1;
3728 USHORT VSyncPolarity:1; //0=Active High, 1=Active Low
3729 USHORT HSyncPolarity:1; //0=Active High, 1=Active Low
3730 USHORT HorizontalCutOff:1;
3732 USHORT HorizontalCutOff:1;
3733 USHORT HSyncPolarity:1; //0=Active High, 1=Active Low
3734 USHORT VSyncPolarity:1; //0=Active High, 1=Active Low
3735 USHORT VerticalCutOff:1;
3736 USHORT H_ReplicationBy2:1;
3737 USHORT V_ReplicationBy2:1;
3738 USHORT CompositeSync:1;
3739 USHORT Interlace:1;
3740 USHORT DoubleClock:1;
3741 USHORT RGB888:1;
3763 #define ATOM_HSYNC_POLARITY 0x02 //0=Active High, 1=Active Low
3764 #define ATOM_VSYNC_POLARITY 0x04 //0=Active High, 1=Active Low
3855 USHORT usPixelClock; //in 10Khz unit
3896 //ucTableFormatRevision=1
3897 //ucTableContentRevision=1
3907 …UCHAR ucLVDS_Misc; // Bit0:{=0:single, =1:dual},Bit1 {=0:666RGB, =1:88…
3908 … // Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888}
3909 … // Bit5:{=0:Spatial Dithering disabled;1 Spatial Dithering enabled}
3910 … // Bit6:{=0:Temporal Dithering disabled;1 Temporal Dithering enabled}
3916 //ucTableFormatRevision=1
3927 …UCHAR ucLVDS_Misc; // Bit0:{=0:single, =1:dual},Bit1 {=0:666RGB, =1:88…
3928 … // Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888}
3929 … // Bit5:{=0:Spatial Dithering disabled;1 Spatial Dithering enabled}
3930 … // Bit6:{=0:Temporal Dithering disabled;1 Temporal Dithering enabled}
3959 // 0 0 1 - 6 Bits per Primary Color
3960 // 0 1 0 - 8 Bits per Primary Color
3961 // 0 1 1 - 10 Bits per Primary Color
3962 // 1 0 0 - 12 Bits per Primary Color
3963 // 1 0 1 - 14 Bits per Primary Color
3964 // 1 1 0 - 16 Bits per Primary Color
3965 // 1 1 1 - Reserved
3969 // Bit7:{=0:Random Dithering disabled;1 Random Dithering enabled}
3985 // ucTableFormatRevision=1
4000 // Bit0: {=0:single, =1:dual},
4001 … // Bit1: {=0:LDI format for RGB888, =1 FPDI format for RGB888} // was {=0:666RGB, =1:888RGB},
4013 … // Bit2: a quick reference whether an embadded panel (LCD1 ) is LVDS (0) or eDP (1)
4053 // 0 0 1 - 6 Bits per Primary Color
4054 // 0 1 0 - 8 Bits per Primary Color
4055 // 0 1 1 - 10 Bits per Primary Color
4056 // 1 0 0 - 12 Bits per Primary Color
4057 // 1 0 1 - 14 Bits per Primary Color
4058 // 1 1 0 - 16 Bits per Primary Color
4059 // 1 1 1 - Reserved
4101 #define LCD_MODE_CAP_BL_OFF 1
4110 UCHAR ucFakeEDIDString[1]; // This actually has ucFakeEdidLength elements.
4120 #define LCD_MODE_PATCH_RECORD_MODE_TYPE 1
4130 //ucTableFormatRevision=1
4135 … ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Bit2=1…
4173 //ATOM_TV_NTSC 1
4209 UCHAR ucMaxLane; //Bits 4:0 = MAX_LANE_COUNT (1/2/4). Bit 7 = ENHANCED_FRAME_CAP
4210 …UCHAR ucMaxDownSpread; //Bit0 = 0: No Down spread; Bit0 = 1: 0.5% (Subject to change acc…
4309 // ucTableFormatRevision=1,ucTableContentRevision=4, the strcuture remains
4329 #define ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO 1
4389 ATOM_GPIO_PIN_ASSIGNMENT asGPIO_Pin[1];
4450 UCHAR ucPinActiveState; //ucPinActiveState: Bit0=1 active high, =0 active low
4465 //ucTableContentRevision=1
4516 …USHORT usGraphicObjIds[1]; //1st Encoder Obj source from GPU to last…
4525 … //usGraphicObjIds[0]= GPU internal encoder, usGraphicObjIds[1]= external encoder
4533 ATOM_DISPLAY_OBJECT_PATH asDispPath[1];
4548 ATOM_OBJECT asObjects[1];
4554 USHORT usSrcObjectID[1];
4556 USHORT usDstObjectID[1];
4563 #define EXT_HPDPIN_LUTINDEX_1 1
4570 #define MAX_NUMBER_OF_EXT_HPDPIN_LUT_ENTRIES (EXT_HPDPIN_LUTINDEX_7+1)
4573 #define EXT_AUXDDC_LUTINDEX_1 1
4580 #define MAX_NUMBER_OF_EXT_AUXDDC_LUT_ENTRIES (EXT_AUXDDC_LUTINDEX_7+1)
4584 //Bit[1:0]: Define which pin connect to DP connector DP_Lane0, =0: source from GPU pin TX0, =1: fro…
4585 //Bit[3:2]: Define which pin connect to DP connector DP_Lane1, =0: source from GPU pin TX0, =1: fro…
4586 //Bit[5:4]: Define which pin connect to DP connector DP_Lane2, =0: source from GPU pin TX0, =1: fro…
4587 //Bit[7:6]: Define which pin connect to DP connector DP_Lane3, =0: source from GPU pin TX0, =1: fro…
4604 //Bit[1:0]: Define which pin connect to DVI connector data Lane2, =0: source from GPU pin TX0, =1: …
4605 //Bit[3:2]: Define which pin connect to DVI connector data Lane1, =0: source from GPU pin TX0, =1: …
4606 //Bit[5:4]: Define which pin connect to DVI connector data Lane0, =0: source from GPU pin TX0, =1: …
4607 //Bit[7:6]: Define which pin connect to DVI connector clock lane, =0: source from GPU pin TX0, =1: …
4636 … // bit vector for up to 8 lanes, =0: P and N is not invert, =1 P and N is inverted
4664 …UCHAR ucFixDPVoltageSwing; // usCaps[1]=1, this indicate DP_L…
4676 #define ATOM_I2C_RECORD_TYPE 1
4736 …ATOM_CONNECTOR_DEVICE_TAG asDeviceTag[1]; //This Id is same as "ATOM_DEVICE_XXX_SUPPORT"…
4744 …UCHAR ucConfigGPIOState; //Set to 1 when it's active high to en…
4753 UCHAR ucCTL1GPIOState; //Set to 1 when it's active high
4755 UCHAR ucCTL2GPIOState; //Set to 1 when it's active high
4757 UCHAR ucCTL3GPIOState; //Set to 1 when it's active high
4766 …UCHAR ucTVActiveState; //Indicating when the pin==0 or 1 when TV is c…
4773 UCHAR ucTMSGPIOState; //Set to 1 when it's active high
4775 UCHAR ucTCKGPIOState; //Set to 1 when it's active high
4777 UCHAR ucTDOGPIOState; //Set to 1 when it's active high
4779 UCHAR ucTDIGPIOState; //Set to 1 when it's active high
4796 …ATOM_GPIO_PIN_CONTROL_PAIR asGpio[1]; // the real gpio pin pair determined by number…
4813 #define ATOM_GPIO_INDEX_GLSYNC_HSYNC 1
4845 USHORT usHBR2En:1; // Bit1 is for DP1.2 HBR2 enable
4846 USHORT usHBR2Cap:1; // Bit0 is for DP1.2 HBR2 capability.
4848 USHORT usHBR2Cap:1; // Bit0 is for DP1.2 HBR2 capability.
4849 USHORT usHBR2En:1; // Bit1 is for DP1.2 HBR2 enable
4865 USHORT usHBR3En:1; // bit3 is for DP1.3 HBR3 enable
4866 …USHORT usHDMI6GEn:1; // Bit2 is for HDMI6Gbps enable, this bit is used st…
4867 USHORT usHBR2En:1; // Bit1 is for DP1.2 HBR2 enable
4868 USHORT usMSTEn:1; // Bit0 is for DP1.2 MST enable
4870 USHORT usMSTEn:1; // Bit0 is for DP1.2 MST enable
4871 USHORT usHBR2En:1; // Bit1 is for DP1.2 HBR2 enable
4872 …USHORT usHDMI6GEn:1; // Bit2 is for HDMI6Gbps enable, this bit is used st…
4873 USHORT usHBR3En:1; // bit3 is for DP1.3 HBR3 enable
4882 #define ATOM_CONNECTOR_CF_RECORD_CONNECTED_UPPER12BITBUNDLEA 1
4912 … //decide the number of ucMuxState, =0, no pin state, =1: single state with complement, >1: mu…
4971 #define CONNECTOR_TYPE_DVI_D 1
4985 ATOM_CONNECTOR_LAYOUT_INFO asConnInfo[1];
5015 USHORT usVoltageBaseLevel; // In number of 1mv unit
5016 …USHORT usVoltageStep; // Indicating in how many mv increament is one step, 1mv …
5018 UCHAR ucFlag; // bit0=0 :step is 1mv =1 0.5mv
5147 UCHAR ucVoltageControlFlag; // Bit0: 0 - One byte data; 1 - Two byte data
5149 VOLTAGE_LUT_ENTRY asVolI2cLut[1]; // end with 0xff
5154 #define VOLTAGE_DATA_TWO_BYTE 1
5164 VOLTAGE_LUT_ENTRY_V2 asVolGpioLut[1];
5174 LEAKAGE_VOLTAGE_LUT_ENTRY_V2 asLeakageIdLut[1];
5185 // 1:0 - offset trim,
5245 #define ATOM_ASIC_PROFILE_ID_EFUSE_VOLTAGE 1
5246 #define ATOM_ASIC_PROFILE_ID_EFUSE_PERFORMANCE_VOLTAGE 1
5272 //Measured = LN((2^Bitsize-1)/EFUSE-1)*(Range)/(-alpha)+(Max+Min)/2
5282 //Linear Function: Measured = Round ( Efuse * ( Max-Min )/(2^BitSize -1 ) + Min )
5402 …USHORT usParamNegFlag; //bit0 =1 :indicate ulRoBeta is Negative, bit1=1 indicate Kv_m ma…
5519 …RAM sRoFuse;//Efuse RO info: DWORD address, bit shift, length, max/min measure value. in unit of 1.
5522 …Model; //def="EVV_SPEED_MODEL" descr="0 = Greek model, 1 = multivariate model" unit="1"/>
5531 …gn; //def="EVV_SM_A0_SIGN" descr="=0 SM_A0 is postive. =1: SM_A0 is negative" unit="1"/>
5532 …gn; //def="EVV_SM_A1_SIGN" descr="=0 SM_A1 is postive. =1: SM_A1 is negative" unit="1"/>
5533 …gn; //def="EVV_SM_A2_SIGN" descr="=0 SM_A2 is postive. =1: SM_A2 is negative" unit="1"/>
5534 …gn; //def="EVV_SM_A3_SIGN" descr="=0 SM_A3 is postive. =1: SM_A3 is negative" unit="1"/>
5535 …gn; //def="EVV_SM_A4_SIGN" descr="=0 SM_A4 is postive. =1: SM_A4 is negative" unit="1"/>
5536 …gn; //def="EVV_SM_A5_SIGN" descr="=0 SM_A5 is postive. =1: SM_A5 is negative" unit="1"/>
5537 …gn; //def="EVV_SM_A6_SIGN" descr="=0 SM_A6 is postive. =1: SM_A6 is negative" unit="1"/>
5538 …gn; //def="EVV_SM_A7_SIGN" descr="=0 SM_A7 is postive. =1: SM_A7 is negative" unit="1"/>
5539 …RO_a; //def="EVV_MARGIN_RO_A" descr="A Term to represent RO equation in Ax2+Bx+C, unit=1"
5540 …RO_b; //def="EVV_MARGIN_RO_B" descr="B Term to represent RO equation in Ax2+Bx+C, unit=1"
5541 …RO_c; //def="EVV_MARGIN_RO_C" descr="C Term to represent RO equation in Ax2+Bx+C, unit=1"
5542 …fixed; //def="EVV_MARGIN_FIXED" descr="Fixed MHz to add to SCLK margin, unit=1" unit="1"/>
5626 UCHAR ucVco_setting; // 1: 3-6GHz, 3: 2-4GHz
5694 ATOM_POWER_SOURCE_OBJECT asPwrObj[1];
5713 …mSupportedCLK; // Maximum clock supported with specified voltage index, unit in 10kHz
5720 …mSupportedCLK; // Maximum clock supported with specified voltage index, unit in 10kHz
5725 …upportedSCLK; // Maximum clock supported with specified voltage index, unit in 10kHz
5731 #define ATOM_IGP_INFO_V6_SYSTEM_CONFIG__PCIE_POWER_GATING_ENABLE 1 // refer to ul…
5809 ulBootUpEngineClock: VBIOS bootup Engine clock frequency, in 10kHz unit. if it is equa…
5810 ulDentistVCOFreq: Dentist VCO clock in 10kHz unit.
5811 ulBootUpUMAClock: System memory boot up clock frequency in 10Khz unit.
5826 =1: TMDS/HDMI Coherent Mode use signel PLL mode.
5828 =1: Disable HW AUX mode dettion logic
5835 …1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determin…
5836 … VBIOS will set up proper PWM frequency and ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1,as the result,
5842 … VBIOS will NOT set up PWM frequency but make ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1
5851 ulMinEngineClock: Minimum SCLK allowed in 10kHz unit. This is calculated based on W…
5853 =1: PCIE Power Gating Enabled
5854 Bit[1]=0: DDR-DLL shut-down feature disabled.
5855 1: DDR-DLL shut-down feature enabled.
5857 1: DDR-PLL Power down feature enabled.
5869 ucMemoryType: [3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved.
5876 … Minimum NCLK speed among all NB-Pstates to calcualte data reconnection latency. Unit in 10kHz.
5877 ulIdleNClk: NCLK speed while memory runs in self-refresh state. Unit in 10kHz.
5880 usPCIEClkSSPercentage: PCIE Clock Spred Spectrum Percentage in unit 0.01%; 100 mean 1%.
5881 usPCIEClkSSType: PCIE Clock Spred Spectrum Type. 0 for Down spread(default); 1 for…
5884 usHDMISSPercentage: HDMI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, …
5886 usDVISSPercentage: DVI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, u…
5889 ucLVDSMisc: [bit0] LVDS 888bit panel mode =0: LVDS 888 panel in LDI mode, =1:…
5890 …panel lower and upper link mapping =0: lower link and upper link not swap, =1: lower link and uppe…
5891 … [bit2] LVDS 888bit per color mode =0: 666 bit per color =1:888 bit per color
5892 …it3] LVDS parameter override enable =0: ucLvdsMisc parameter are not used =1: ucLvdsMisc paramete…
5893 …y of signal sent to digital BLON output pin. =0: not inverted(active high) =1: inverted ( active l…
6021 //ulGPUCapInfo[16]=1 indicate SMC firmware is able to support GNB fast resume function, so that dri…
6024 //ulGPUCapInfo[17]=1 indicate battery boost feature is enable, from ML
6029 ulBootUpEngineClock: VBIOS bootup Engine clock frequency, in 10kHz unit. if it is equa…
6030 ulDentistVCOFreq: Dentist VCO clock in 10kHz unit.
6031 ulBootUpUMAClock: System memory boot up clock frequency in 10Khz unit.
6043 ulOtherDisplayMisc: bit[0]=0: INT15 callback function Get LCD EDID ( ax=4e08, bl=1b…
6044 … =1: INT15 callback function Get LCD EDID ( ax=4e08, bl=1b ) is supported by SBIOS.
6045 … bit[1]=0: INT15 callback function Get boot display( ax=4e08, bl=01h) is not supported by SBIOS
6046 … =1: INT15 callback function Get boot display( ax=4e08, bl=01h) is supported by SBIOS
6048 … =1: INT15 callback function Get panel Expansion ( ax=4e08, bl=02h) is supported by SBIOS
6050 …=1: VBIOS fast boot is enable. ( VBIOS skip display device detection in every set mode if LCD pane…
6052 =1: TMDS/HDMI Coherent Mode use signel PLL mode.
6053 bit[1]=0: DP mode use cascade PLL mode ( New for Trinity )
6054 =1: DP mode use single PLL mode
6056 =1: Disable AUX HW mode detection logic
6064 …1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determin…
6065 … VBIOS will set up proper PWM frequency and ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1,as the result,
6071 … VBIOS will NOT set up PWM frequency but make ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1
6080 ulMinEngineClock: Minimum SCLK allowed in 10kHz unit. This is calculated based on W…
6082 =1: PCIE Power Gating Enabled
6083 Bit[1]=0: DDR-DLL shut-down feature disabled.
6084 1: DDR-DLL shut-down feature enabled.
6086 1: DDR-PLL Power down feature enabled.
6100 ucMemoryType: [3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved.
6107 … Minimum NCLK speed among all NB-Pstates to calcualte data reconnection latency. Unit in 10kHz.
6108 ulIdleNClk: NCLK speed while memory runs in self-refresh state. Unit in 10kHz.
6111 usPCIEClkSSPercentage: PCIE Clock Spread Spectrum Percentage in unit 0.01%; 100 mean 1%.
6112 usPCIEClkSSType: PCIE Clock Spread Spectrum Type. 0 for Down spread(default); 1 fo…
6115 usHDMISSPercentage: HDMI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, …
6117 usDVISSPercentage: DVI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, u…
6120 ucLVDSMisc: [bit0] LVDS 888bit panel mode =0: LVDS 888 panel in LDI mode, =1:…
6121 …panel lower and upper link mapping =0: lower link and upper link not swap, =1: lower link and uppe…
6122 … [bit2] LVDS 888bit per color mode =0: 666 bit per color =1:888 bit per color
6123 …it3] LVDS parameter override enable =0: ucLvdsMisc parameter are not used =1: ucLvdsMisc paramete…
6124 …y of signal sent to digital BLON output pin. =0: not inverted(active high) =1: inverted ( active l…
6125 …[bit5] Travid LVDS output voltage override enable, when =1, use ucTravisLVDSVolAdjust value to ove…
6126 ucTravisLVDSVolAdjust When ucLVDSMisc[5]=1,it means platform SBIOS want to overwrite Tr…
6159 ulNbpStateMemclkFreq[4]: system memory clock frequncey in unit of 10Khz in different NB ps…
6231 ulBootUpEngineClock: VBIOS bootup Engine clock frequency, in 10kHz unit. if it is equa…
6232 ulDentistVCOFreq: Dentist VCO clock in 10kHz unit.
6233 ulBootUpUMAClock: System memory boot up clock frequency in 10Khz unit.
6247 … bit[0]=0: INT15 callback function Get LCD EDID ( ax=4e08, bl=1b ) is not supported by SBIOS.
6248 … =1: INT15 callback function Get LCD EDID ( ax=4e08, bl=1b ) is supported by SBIOS.
6249 … bit[1]=0: INT15 callback function Get boot display( ax=4e08, bl=01h) is not supported by SBIOS
6250 … =1: INT15 callback function Get boot display( ax=4e08, bl=01h) is supported by SBIOS
6252 … =1: INT15 callback function Get panel Expansion ( ax=4e08, bl=02h) is supported by SBIOS
6254 …=1: VBIOS fast boot is enable. ( VBIOS skip display device detection in every set mode if LCD pane…
6258 =1: Disable AUX HW mode detection logic
6260 =1: Enable DFS bypass feature
6266 …1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determin…
6267 … VBIOS will set up proper PWM frequency and ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1,as the result,
6273 … VBIOS will NOT set up PWM frequency but make ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1
6283 =1: PCIE Power Gating Enabled
6284 Bit[1]=0: DDR-DLL shut-down feature disabled.
6285 1: DDR-DLL shut-down feature enabled.
6287 1: DDR-PLL Power down feature enabled.
6289 =1: GNB DPM is enabled
6300 ucMemoryType: [3:0]=1:DDR1;=2:DDR2;=3:DDR3;=5:GDDR5; [7:4] is reserved.
6308 …eed while memory runs in self-refresh state, used to calculate self-refresh latency. Unit in 10kHz.
6312 usPCIEClkSSPercentage: PCIE Clock Spread Spectrum Percentage in unit 0.01%; 100 mean 1%.
6313 usPCIEClkSSType: PCIE Clock Spread Spectrum Type. 0 for Down spread(default); 1 fo…
6316 usHDMISSPercentage: HDMI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, …
6318 usDVISSPercentage: DVI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, u…
6326 ucLVDSMisc: [bit0] LVDS 888bit panel mode =0: LVDS 888 panel in LDI mode, =1:…
6327 …panel lower and upper link mapping =0: lower link and upper link not swap, =1: lower link and uppe…
6328 … [bit2] LVDS 888bit per color mode =0: 666 bit per color =1:888 bit per color
6329 …it3] LVDS parameter override enable =0: ucLvdsMisc parameter are not used =1: ucLvdsMisc paramete…
6330 …y of signal sent to digital BLON output pin. =0: not inverted(active high) =1: inverted ( active l…
6331 …[bit5] Travid LVDS output voltage override enable, when =1, use ucTravisLVDSVolAdjust value to ove…
6332 ucTravisLVDSVolAdjust When ucLVDSMisc[5]=1,it means platform SBIOS want to overwrite Tr…
6367 ulNbpStateMemclkFreq[4]: system memory clock frequncey in unit of 10Khz in different NB P-…
6454 #define EDP_VS_LOW_VDIFF_MODE 1
6464 //ulGPUCapInfo[16]=1 indicate SMC firmware is able to support GNB fast resume function, so that dri…
6466 //ulGPUCapInfo[18]=1 indicate the IOMMU is not available
6468 //ulGPUCapInfo[19]=1 indicate the MARC Aperture is opened.
6485 UCHAR ucID; // 0: Rear, 1: Front right of user, 2: Front left of user
6492 UCHAR ucID; // 0: Rear, 1: Front
6500 FLASHLIGHT_INFO asFlashInfo; // Assuming 1 flashlight max
6595 #define ICS91719 1
6602 …UCHAR ucI2CData[1]; //I2C data in bytes, s…
6613 ATOM_I2C_DATA_RECORD asI2CData[1];
6620 ATOM_I2C_DEVICE_SETUP_INFO asI2CSetup[1];
6631 … ulTargetClockRange; //Clock Out frequence (VCO ), in unit of 10Khz
6633 USHORT usSpreadRateInKhz; //in unit of kHz, modulation freq
6635 …UCHAR ucSpreadSpectrumMode; //Bit1=0 Down Spread,=1 Center Sp…
6641 #define ASIC_INTERNAL_MEMORY_SS 1
6656 …rgetClockRange; //For mem/engine/uvd, Clock Out frequence (VCO ), in unit of 10Khz
6661 …preadSpectrumMode; //Bit0=0 Down Spread,=1 Center Spread, bit1=0: internal SS bit1=1…
6682 ATOM_ASIC_SS_ASSIGNMENT_V2 asSpreadSpectrum[1]; //this is point only.
6687 …rgetClockRange; //For mem/engine/uvd, Clock Out frequence (VCO ), in unit of 10Khz
6692 …preadSpectrumMode; //Bit0=0 Down Spread,=1 Center Spread, bit1=0: internal SS bit1=1…
6704 ATOM_ASIC_SS_ASSIGNMENT_V3 asSpreadSpectrum[1]; //this is pointer only.
6710 #define ATOM_ROM_LOCATION_DEF 1
6769 #define ATOM_S0_SYSTEM_POWER_STATE_VALUE_AC 1
7046 #define ATOM_S6_SCALER_CHANGE_SHIFT 1
7171 ULONG ulTargetMemoryClock; //In 10Khz unit
7197 UCHAR ucPadding[1];
7203 #define SCALER_BYPASS_AUTO_CENTER_AUTO_REPLICATION 1
7226 UCHAR ucSurface; // Surface 1 or 2
7234 UCHAR ucSurface; // Surface 1 or 2
7243 UCHAR ucSurface; // Surface 1 or 2
7255 UCHAR ucSurface; // Surface 1 or 2
7307 #define PALETTE_DATA_AUTO_FILL 1
7321 #define HDP1_INTERRUPT_ID 1
7330 #define INTERRUPT_SERVICE_GEN_SW_INT 1
7334 #define INTERRUPT_STATUS__INT_TRIGGER 1
7361 #define INDIRECT_IO_PLL 1
7468 ULONG aulMemData[1];
7481 ATOM_INIT_REG_INDEX_FORMAT asRegIndexBuf[1];
7482 ATOM_MEMORY_SETTING_DATA_BLOCK asRegDataBuf[1];
7494 #define INDEX_ACCESS_RANGE_BEGIN (VALUE_DWORD + 1)
7495 #define INDEX_ACCESS_RANGE_END (INDEX_ACCESS_RANGE_BEGIN + 1)
7496 #define VALUE_INDEX_ACCESS_SINGLE (INDEX_ACCESS_RANGE_END + 1)
7651 …ULONG ulClkRange; // memory clock in 10kHz unit, when target memory…
7687 …ULONG ulClkRange; // memory clock in 10kHz unit, when target memor…
7723 …ULONG ulClkRange; // memory clock in 10kHz unit, when …
7775 …UCHAR ucBurstSize; // burst size, 0= burst size=4 1= burst size=8
7817 UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits
7820 … // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlength 4, 1…
7838 …UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64…
7859 UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits
7862 … // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlength 4, 1…
7874 …UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64…
7891 UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits
7894 … // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlength 4, 1…
7906 …UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64…
7936 …UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
7955 … // bit[3:2]= BANK ( =2:16bank, =1:8bank, =0:4bank ) bit[1:0]=Col ( =2: 10 bit,…
7966 …UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
8005 … // DQ line byte remap, =0: Memory Data line BYTE0, =1: BYTE1, =2: BYTE2, =…
8106 #define SW_I2C_IO_GET 1
8118 #define SW_I2C_CNTL_WRITE 1
8214 UCHAR ReservedForPageFunction;//db 1 ; reserved for page function
8303 UCHAR ucEncoderID; //available 1st encoder ( default )
8331 ASIC_TRANSMITTER_INFO asTransmitterInfo[1];
8332 ASIC_ENCODER_INFO asEncoderInfo[1];
8342 ASIC_TRANSMITTER_INFO asTransmitterInfo[1];
8343 ASIC_ENCODER_INFO asEncoderInfo[1];
8364 UCHAR ucEncoderID; // available 1st encoder ( default )
8384 ASIC_TRANSMITTER_INFO_V2 asTransmitterInfo[1]; // for alligment only
8393 CLOCK_SRC_XO_IN=1,
8431 …UCHAR ucHPD_ID; //=0: HPD1, =1: HPD2, =2: HPD3, =3: HPD4, …
8513 #define HW_I2C_WRITE 1
8539 #define ATOM_FEATURE_NOT_SUPPORTED 1
8552 UCHAR ucHWBlkInst; // HW block instance, 0, 1, 2, ...
8562 #define SELECT_DISP_PLL 1
8620 ULONG ulAnalogSetting[1];
8625 CLOCK_CONDITION_SETTING_ENTRY asClkCondSettingEntry[1];
8642 PHY_CONDITION_REG_VAL asRegVal[1];
8648 PHY_CONDITION_REG_VAL_V2 asRegVal[1];
8655 PHY_CONDITION_REG_INFO asAnalogSetting[1];
8662 PHY_CONDITION_REG_INFO_V2 asAnalogSetting[1];
8675 #define GFX_HARVESTING_RB_ID 1
8737 USHORT usMaxFrequency; // in 10kHz unit
8755 …UCHAR ucDAC2_CRT2_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active L…
8760 …UCHAR ucDAC2_TV1_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active L…
8765 …UCHAR ucDAC2_CV_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active L…
8774 // = 1 - VGA connector
8789 // = 1 - DACA
8868 USHORT usMaxFrequency; // in 10Khz
8876 UCHAR ucPadding[1];
8882 UCHAR ucPadding[1];
8908 #define ATOM_XTMDS_ASIC_SI164_ID 1
8922 …UCHAR ucSupportedLink; // Bit field, bit0=1, single link supported;bit1=1,…
8966 #define ATOM_PM_MISCINFO_FRAME_MODULATION_MASK 0x00300000L //0-FM Disable, 1-2 level FM,…
8976 #define ATOM_PM_MISCINFO_POWERPLAY_SETTINGS_GROUP_MASK 0x70000000L //1-Optimal Battery Life Grou…
8992 //ucTableFormatRevision=1
8993 //ucTableContentRevision=1
9009 //ucTableContentRevision=1
9211 #pragma pack(1)
9223 UCHAR ucSignatureType; // Signature type ( 0 - no signature, 1 - test, 2 - production )
9235 ATOM_HOLE_INFO holes[1]; // array of hole descriptions
9245 #pragma pack(1)
9295 UCHAR VbiosContent[1];
9300 UCHAR Lib1Content[1];