Lines Matching +full:dc +full:- +full:dc
2 * Copyright 2012-14 Advanced Micro Devices, Inc.
102 // for example, 1080p -> 8K is 4.0, or 4000 raw value
110 // for example, 8K -> 1080p is 0.25, or 250 raw value
122 * DOC: color-management-caps
127 * abstracted HW. DCE 5-12 had almost no important changes, but starting with
134 * struct rom_curve_caps - predefined transfer function caps for degamma and regamma
150 * struct dpp_color_caps - color pipeline capabilities for display pipe and
155 * just plain 256-entry lookup
164 * @dgam_rom_for_yuv: pre-defined degamma LUT for YUV planes
165 * @dgam_rom_caps: pre-definied curve caps for degamma 1D LUT
166 * @ogam_rom_caps: pre-definied curve caps for regamma 1D LUT
186 * struct mpc_color_caps - color pipeline capabilities for multiple pipe and
195 * @ogam_rom_caps: pre-definied curve caps for regamma 1D LUT
207 * struct dc_color_caps - color pipes capabilities for DPP and MPC hw blocks
338 * re-programming however do not affect bandwidth consumption or clock
360 struct dc;
366 bool (*get_dcc_compression_cap)(const struct dc *dc,
381 /* Structure to hold configuration flags set by dm at dc creation. */
446 * enum pipe_split_policy - Pipe split strategy supported by DCN
449 * default, DC favors MPC_SPLIT_DYNAMIC.
453 * @MPC_SPLIT_DYNAMIC: DC will automatically decide how to split the
454 * pipe in order to bring the best trade-off between performance and
460 * @MPC_SPLIT_DYNAMIC: Avoid pipe split, which means that DC will not
466 * @MPC_SPLIT_DYNAMIC: With this option, DC will only try to optimize
468 * connects to a second display, DC will avoid pipe split.
486 DCN_PWR_STATE_UNKNOWN = -1,
554 unsigned long long start_tick = dc->debug.bw_val_profile.enable ? \
555 dm_get_timestamp(dc->ctx) : 0
558 if (dc->debug.bw_val_profile.enable) \
559 dc->debug.bw_val_profile.total_count++
562 if (dc->debug.bw_val_profile.enable) { \
564 voltage_level_tick = dm_get_timestamp(dc->ctx); \
565 dc->debug.bw_val_profile.skip_ ## status ## _count++; \
569 if (dc->debug.bw_val_profile.enable) \
570 voltage_level_tick = dm_get_timestamp(dc->ctx)
573 if (dc->debug.bw_val_profile.enable) \
574 watermark_tick = dm_get_timestamp(dc->ctx)
577 if (dc->debug.bw_val_profile.enable) { \
578 end_tick = dm_get_timestamp(dc->ctx); \
579 dc->debug.bw_val_profile.total_ticks += end_tick - start_tick; \
580 dc->debug.bw_val_profile.voltage_level_ticks += voltage_level_tick - start_tick; \
582 dc->debug.bw_val_profile.watermark_ticks += watermark_tick - voltage_level_tick; \
583 dc->debug.bw_val_profile.rq_dlg_ticks += end_tick - watermark_tick; \
634 * 15-2: reserved
635 * 31-16: timeout in ms
705 * struct dc_debug_options - DC debug struct
810 /* TODO - remove once tested */
860 struct dc { struct
981 struct dc *dc_create(const struct dc_init_data *init_params);
982 void dc_hardware_init(struct dc *dc);
984 int dc_get_vmid_use_vector(struct dc *dc);
985 void dc_setup_vm_context(struct dc *dc, struct dc_virtual_addr_space_config *va_config, int vmid);
987 int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config);
988 void dc_init_callbacks(struct dc *dc,
990 void dc_deinit_callbacks(struct dc *dc);
991 void dc_destroy(struct dc **dc);
1183 /* private to DC core */
1250 struct dc_plane_state *dc_create_plane_state(struct dc *dc);
1270 struct dc *dc);
1283 bool dc_validate_boot_timing(const struct dc *dc,
1287 enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state);
1299 struct dc *dc,
1305 const struct dc *dc,
1309 struct dc *dc, bool acquire,
1319 const struct dc *dc,
1324 bool dc_resource_is_dsc_encoding_supported(const struct dc *dc);
1335 bool dc_commit_state(struct dc *dc, struct dc_state *context);
1337 struct dc_state *dc_create_state(struct dc *dc);
1365 indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/
1401 /* 0 - Sink supports backlight adjust via PWM during SDR/HDR mode
1402 * 1 - Sink supports backlight adjust via AUX during SDR/HDR mode.
1444 uint32_t dc_get_opp_for_plane(struct dc *dc, struct dc_plane_state *plane);
1447 * Sink Interfaces - A sink corresponds to a display output device
1453 // 8 byte port ID -> ELD.PortID
1455 // 128bit GUID in binary formufacturer name -> ELD.ManufacturerName
1457 // 2 byte product code -> ELD.ProductCode
1497 /* private to DC core */
1520 bool dc_extended_blank_supported(struct dc *dc);
1535 struct dc *dc,
1538 bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable);
1539 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src);
1541 struct dc *dc, uint32_t link_index);
1543 void dc_notify_vsync_int_state(struct dc *dc, struct dc_stream_state *stream, bool enable);
1550 struct dc *dc,
1552 void dc_resume(struct dc *dc);
1554 void dc_power_down_on_boot(struct dc *dc);
1565 bool dc_is_dmcu_initialized(struct dc *dc);
1567 enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_…
1568 void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg);
1570 bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc, struct dc_plane_state *plane,
1573 void dc_allow_idle_optimizations(struct dc *dc, bool allow);
1576 void dc_unlock_memory_clock_frequency(struct dc *dc);
1579 void dc_lock_memory_clock_frequency(struct dc *dc);
1581 /* set soft max for memclk, to be used for AC/DC switching clock limitations */
1582 void dc_enable_dcmode_clk_limit(struct dc *dc, bool enable);
1585 void dc_hardware_release(struct dc *dc);
1588 void dc_mclk_switch_using_fw_based_vblank_stretch_shut_down(struct dc *dc);
1590 bool dc_set_psr_allow_active(struct dc *dc, bool enable);
1591 void dc_z10_restore(const struct dc *dc);
1592 void dc_z10_save_init(struct dc *dc);
1594 bool dc_is_dmub_outbox_supported(struct dc *dc);
1595 bool dc_enable_dmub_notifications(struct dc *dc);
1597 void dc_enable_dmub_outbox(struct dc *dc);
1599 bool dc_process_dmub_aux_transfer_async(struct dc *dc,
1603 /* Get dc link index from dpia port index */
1604 uint8_t get_link_index_from_dpia_port_index(const struct dc *dc,
1607 bool dc_process_dmub_set_config_async(struct dc *dc,
1612 enum dc_status dc_process_dmub_set_mst_slots(const struct dc *dc,
1617 void dc_process_dmub_dpia_hpd_int_enable(const struct dc *dc,
1628 void dc_disable_accelerated_mode(struct dc *dc);