Lines Matching refs:adev
261 static int vi_query_video_codecs(struct amdgpu_device *adev, bool encode, in vi_query_video_codecs() argument
264 switch (adev->asic_type) { in vi_query_video_codecs()
302 static u32 vi_pcie_rreg(struct amdgpu_device *adev, u32 reg) in vi_pcie_rreg() argument
307 spin_lock_irqsave(&adev->pcie_idx_lock, flags); in vi_pcie_rreg()
311 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); in vi_pcie_rreg()
315 static void vi_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v) in vi_pcie_wreg() argument
319 spin_lock_irqsave(&adev->pcie_idx_lock, flags); in vi_pcie_wreg()
324 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); in vi_pcie_wreg()
327 static u32 vi_smc_rreg(struct amdgpu_device *adev, u32 reg) in vi_smc_rreg() argument
332 spin_lock_irqsave(&adev->smc_idx_lock, flags); in vi_smc_rreg()
335 spin_unlock_irqrestore(&adev->smc_idx_lock, flags); in vi_smc_rreg()
339 static void vi_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v) in vi_smc_wreg() argument
343 spin_lock_irqsave(&adev->smc_idx_lock, flags); in vi_smc_wreg()
346 spin_unlock_irqrestore(&adev->smc_idx_lock, flags); in vi_smc_wreg()
353 static u32 cz_smc_rreg(struct amdgpu_device *adev, u32 reg) in cz_smc_rreg() argument
358 spin_lock_irqsave(&adev->smc_idx_lock, flags); in cz_smc_rreg()
361 spin_unlock_irqrestore(&adev->smc_idx_lock, flags); in cz_smc_rreg()
365 static void cz_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v) in cz_smc_wreg() argument
369 spin_lock_irqsave(&adev->smc_idx_lock, flags); in cz_smc_wreg()
372 spin_unlock_irqrestore(&adev->smc_idx_lock, flags); in cz_smc_wreg()
375 static u32 vi_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg) in vi_uvd_ctx_rreg() argument
380 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags); in vi_uvd_ctx_rreg()
383 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags); in vi_uvd_ctx_rreg()
387 static void vi_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v) in vi_uvd_ctx_wreg() argument
391 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags); in vi_uvd_ctx_wreg()
394 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags); in vi_uvd_ctx_wreg()
397 static u32 vi_didt_rreg(struct amdgpu_device *adev, u32 reg) in vi_didt_rreg() argument
402 spin_lock_irqsave(&adev->didt_idx_lock, flags); in vi_didt_rreg()
405 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); in vi_didt_rreg()
409 static void vi_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) in vi_didt_wreg() argument
413 spin_lock_irqsave(&adev->didt_idx_lock, flags); in vi_didt_wreg()
416 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); in vi_didt_wreg()
419 static u32 vi_gc_cac_rreg(struct amdgpu_device *adev, u32 reg) in vi_gc_cac_rreg() argument
424 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags); in vi_gc_cac_rreg()
427 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags); in vi_gc_cac_rreg()
431 static void vi_gc_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v) in vi_gc_cac_wreg() argument
435 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags); in vi_gc_cac_wreg()
438 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags); in vi_gc_cac_wreg()
489 static void vi_init_golden_registers(struct amdgpu_device *adev) in vi_init_golden_registers() argument
492 mutex_lock(&adev->grbm_idx_mutex); in vi_init_golden_registers()
494 if (amdgpu_sriov_vf(adev)) { in vi_init_golden_registers()
495 xgpu_vi_init_golden_registers(adev); in vi_init_golden_registers()
496 mutex_unlock(&adev->grbm_idx_mutex); in vi_init_golden_registers()
500 switch (adev->asic_type) { in vi_init_golden_registers()
502 amdgpu_device_program_register_sequence(adev, in vi_init_golden_registers()
507 amdgpu_device_program_register_sequence(adev, in vi_init_golden_registers()
512 amdgpu_device_program_register_sequence(adev, in vi_init_golden_registers()
517 amdgpu_device_program_register_sequence(adev, in vi_init_golden_registers()
522 amdgpu_device_program_register_sequence(adev, in vi_init_golden_registers()
533 mutex_unlock(&adev->grbm_idx_mutex); in vi_init_golden_registers()
544 static u32 vi_get_xclk(struct amdgpu_device *adev) in vi_get_xclk() argument
546 u32 reference_clock = adev->clock.spll.reference_freq; in vi_get_xclk()
549 if (adev->flags & AMD_IS_APU) in vi_get_xclk()
576 void vi_srbm_select(struct amdgpu_device *adev, in vi_srbm_select() argument
587 static void vi_vga_set_state(struct amdgpu_device *adev, bool state) in vi_vga_set_state() argument
592 static bool vi_read_disabled_bios(struct amdgpu_device *adev) in vi_read_disabled_bios() argument
602 if (adev->mode_info.num_crtc) { in vi_read_disabled_bios()
611 if (adev->mode_info.num_crtc) { in vi_read_disabled_bios()
624 r = amdgpu_read_bios(adev); in vi_read_disabled_bios()
628 if (adev->mode_info.num_crtc) { in vi_read_disabled_bios()
637 static bool vi_read_bios_from_rom(struct amdgpu_device *adev, in vi_read_bios_from_rom() argument
649 if (adev->flags & AMD_IS_APU) in vi_read_bios_from_rom()
655 spin_lock_irqsave(&adev->smc_idx_lock, flags); in vi_read_bios_from_rom()
663 spin_unlock_irqrestore(&adev->smc_idx_lock, flags); in vi_read_bios_from_rom()
747 static uint32_t vi_get_register_value(struct amdgpu_device *adev, in vi_get_register_value() argument
758 return adev->gfx.config.rb_config[se_idx][sh_idx].rb_backend_disable; in vi_get_register_value()
760 return adev->gfx.config.rb_config[se_idx][sh_idx].user_rb_backend_disable; in vi_get_register_value()
762 return adev->gfx.config.rb_config[se_idx][sh_idx].raster_config; in vi_get_register_value()
764 return adev->gfx.config.rb_config[se_idx][sh_idx].raster_config_1; in vi_get_register_value()
767 mutex_lock(&adev->grbm_idx_mutex); in vi_get_register_value()
769 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); in vi_get_register_value()
774 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); in vi_get_register_value()
775 mutex_unlock(&adev->grbm_idx_mutex); in vi_get_register_value()
782 return adev->gfx.config.gb_addr_config; in vi_get_register_value()
784 return adev->gfx.config.mc_arb_ramcfg; in vi_get_register_value()
818 return adev->gfx.config.tile_mode_array[idx]; in vi_get_register_value()
836 return adev->gfx.config.macrotile_mode_array[idx]; in vi_get_register_value()
843 static int vi_read_register(struct amdgpu_device *adev, u32 se_num, in vi_read_register() argument
855 *value = vi_get_register_value(adev, indexed, se_num, sh_num, in vi_read_register()
871 static int vi_asic_pci_config_reset(struct amdgpu_device *adev) in vi_asic_pci_config_reset() argument
876 amdgpu_atombios_scratch_regs_engine_hung(adev, true); in vi_asic_pci_config_reset()
879 pci_clear_master(adev->pdev); in vi_asic_pci_config_reset()
881 amdgpu_device_pci_config_reset(adev); in vi_asic_pci_config_reset()
886 for (i = 0; i < adev->usec_timeout; i++) { in vi_asic_pci_config_reset()
889 pci_set_master(adev->pdev); in vi_asic_pci_config_reset()
890 adev->has_hw_reset = true; in vi_asic_pci_config_reset()
897 amdgpu_atombios_scratch_regs_engine_hung(adev, false); in vi_asic_pci_config_reset()
902 static bool vi_asic_supports_baco(struct amdgpu_device *adev) in vi_asic_supports_baco() argument
904 switch (adev->asic_type) { in vi_asic_supports_baco()
911 return amdgpu_dpm_is_baco_supported(adev); in vi_asic_supports_baco()
918 vi_asic_reset_method(struct amdgpu_device *adev) in vi_asic_reset_method() argument
927 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n", in vi_asic_reset_method()
930 switch (adev->asic_type) { in vi_asic_reset_method()
937 baco_reset = amdgpu_dpm_is_baco_supported(adev); in vi_asic_reset_method()
959 static int vi_asic_reset(struct amdgpu_device *adev) in vi_asic_reset() argument
964 if (adev->flags & AMD_IS_APU) in vi_asic_reset()
967 if (vi_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) { in vi_asic_reset()
968 dev_info(adev->dev, "BACO reset\n"); in vi_asic_reset()
969 r = amdgpu_dpm_baco_reset(adev); in vi_asic_reset()
971 dev_info(adev->dev, "PCI CONFIG reset\n"); in vi_asic_reset()
972 r = vi_asic_pci_config_reset(adev); in vi_asic_reset()
978 static u32 vi_get_config_memsize(struct amdgpu_device *adev) in vi_get_config_memsize() argument
983 static int vi_set_uvd_clock(struct amdgpu_device *adev, u32 clock, in vi_set_uvd_clock() argument
990 r = amdgpu_atombios_get_clock_dividers(adev, in vi_set_uvd_clock()
998 if (adev->flags & AMD_IS_APU) in vi_set_uvd_clock()
1008 if (adev->flags & AMD_IS_APU) { in vi_set_uvd_clock()
1029 static int vi_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) in vi_set_uvd_clocks() argument
1033 if (adev->flags & AMD_IS_APU) { in vi_set_uvd_clocks()
1034 r = vi_set_uvd_clock(adev, vclk, ixGNB_CLK2_DFS_CNTL, ixGNB_CLK2_STATUS); in vi_set_uvd_clocks()
1038 r = vi_set_uvd_clock(adev, dclk, ixGNB_CLK1_DFS_CNTL, ixGNB_CLK1_STATUS); in vi_set_uvd_clocks()
1042 r = vi_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS); in vi_set_uvd_clocks()
1046 r = vi_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS); in vi_set_uvd_clocks()
1054 static int vi_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) in vi_set_vce_clocks() argument
1064 if (adev->flags & AMD_IS_APU) { in vi_set_vce_clocks()
1076 r = amdgpu_atombios_get_clock_dividers(adev, in vi_set_vce_clocks()
1108 static void vi_pcie_gen3_enable(struct amdgpu_device *adev) in vi_pcie_gen3_enable() argument
1110 if (pci_is_root_bus(adev->pdev->bus)) in vi_pcie_gen3_enable()
1116 if (adev->flags & AMD_IS_APU) in vi_pcie_gen3_enable()
1119 if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 | in vi_pcie_gen3_enable()
1126 static void vi_enable_aspm(struct amdgpu_device *adev) in vi_enable_aspm() argument
1152 static void vi_program_aspm(struct amdgpu_device *adev) in vi_program_aspm() argument
1158 if (!amdgpu_device_should_use_aspm(adev) || !aspm_support_quirk_check()) in vi_program_aspm()
1161 if (adev->flags & AMD_IS_APU || in vi_program_aspm()
1162 adev->asic_type < CHIP_POLARIS10) in vi_program_aspm()
1190 pci_read_config_dword(adev->pdev, PCIE_L1_PM_SUB_CNTL, &data1); in vi_program_aspm()
1214 pci_read_config_dword(adev->pdev, LINK_CAP, &data); in vi_program_aspm()
1288 vi_enable_aspm(adev); in vi_program_aspm()
1301 if ((adev->asic_type == CHIP_POLARIS12 && in vi_program_aspm()
1302 !(ASICID_IS_P23(adev->pdev->device, adev->pdev->revision))) || in vi_program_aspm()
1303 ASIC_IS_P22(adev->asic_type, adev->external_rev_id)) { in vi_program_aspm()
1311 static void vi_enable_doorbell_aperture(struct amdgpu_device *adev, in vi_enable_doorbell_aperture() argument
1317 if (adev->flags & AMD_IS_APU) in vi_enable_doorbell_aperture()
1333 static uint32_t vi_get_rev_id(struct amdgpu_device *adev) in vi_get_rev_id() argument
1335 if (adev->flags & AMD_IS_APU) in vi_get_rev_id()
1343 static void vi_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring) in vi_flush_hdp() argument
1353 static void vi_invalidate_hdp(struct amdgpu_device *adev, in vi_invalidate_hdp() argument
1364 static bool vi_need_full_reset(struct amdgpu_device *adev) in vi_need_full_reset() argument
1366 switch (adev->asic_type) { in vi_need_full_reset()
1385 static void vi_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0, in vi_get_pcie_usage() argument
1395 if (adev->flags & AMD_IS_APU) in vi_get_pcie_usage()
1431 static uint64_t vi_get_pcie_replay_count(struct amdgpu_device *adev) in vi_get_pcie_replay_count() argument
1443 static bool vi_need_reset_on_init(struct amdgpu_device *adev) in vi_need_reset_on_init() argument
1447 if (adev->flags & AMD_IS_APU) in vi_need_reset_on_init()
1460 static void vi_pre_asic_init(struct amdgpu_device *adev) in vi_pre_asic_init() argument
1493 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in vi_common_early_init() local
1495 if (adev->flags & AMD_IS_APU) { in vi_common_early_init()
1496 adev->smc_rreg = &cz_smc_rreg; in vi_common_early_init()
1497 adev->smc_wreg = &cz_smc_wreg; in vi_common_early_init()
1499 adev->smc_rreg = &vi_smc_rreg; in vi_common_early_init()
1500 adev->smc_wreg = &vi_smc_wreg; in vi_common_early_init()
1502 adev->pcie_rreg = &vi_pcie_rreg; in vi_common_early_init()
1503 adev->pcie_wreg = &vi_pcie_wreg; in vi_common_early_init()
1504 adev->uvd_ctx_rreg = &vi_uvd_ctx_rreg; in vi_common_early_init()
1505 adev->uvd_ctx_wreg = &vi_uvd_ctx_wreg; in vi_common_early_init()
1506 adev->didt_rreg = &vi_didt_rreg; in vi_common_early_init()
1507 adev->didt_wreg = &vi_didt_wreg; in vi_common_early_init()
1508 adev->gc_cac_rreg = &vi_gc_cac_rreg; in vi_common_early_init()
1509 adev->gc_cac_wreg = &vi_gc_cac_wreg; in vi_common_early_init()
1511 adev->asic_funcs = &vi_asic_funcs; in vi_common_early_init()
1513 adev->rev_id = vi_get_rev_id(adev); in vi_common_early_init()
1514 adev->external_rev_id = 0xFF; in vi_common_early_init()
1515 switch (adev->asic_type) { in vi_common_early_init()
1517 adev->cg_flags = 0; in vi_common_early_init()
1518 adev->pg_flags = 0; in vi_common_early_init()
1519 adev->external_rev_id = 0x1; in vi_common_early_init()
1522 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in vi_common_early_init()
1539 adev->pg_flags = 0; in vi_common_early_init()
1540 adev->external_rev_id = adev->rev_id + 0x3c; in vi_common_early_init()
1543 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in vi_common_early_init()
1556 adev->pg_flags = 0; in vi_common_early_init()
1557 adev->external_rev_id = adev->rev_id + 0x14; in vi_common_early_init()
1560 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in vi_common_early_init()
1579 adev->pg_flags = 0; in vi_common_early_init()
1580 adev->external_rev_id = adev->rev_id + 0x5A; in vi_common_early_init()
1583 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in vi_common_early_init()
1602 adev->pg_flags = 0; in vi_common_early_init()
1603 adev->external_rev_id = adev->rev_id + 0x50; in vi_common_early_init()
1606 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in vi_common_early_init()
1625 adev->pg_flags = 0; in vi_common_early_init()
1626 adev->external_rev_id = adev->rev_id + 0x64; in vi_common_early_init()
1629 adev->cg_flags = 0; in vi_common_early_init()
1649 adev->pg_flags = 0; in vi_common_early_init()
1650 adev->external_rev_id = adev->rev_id + 0x6E; in vi_common_early_init()
1653 adev->cg_flags = AMD_CG_SUPPORT_UVD_MGCG | in vi_common_early_init()
1669 adev->pg_flags = 0; in vi_common_early_init()
1670 if (adev->rev_id != 0x00 || CZ_REV_BRISTOL(adev->pdev->revision)) { in vi_common_early_init()
1671 adev->pg_flags |= AMD_PG_SUPPORT_GFX_SMG | in vi_common_early_init()
1677 adev->external_rev_id = adev->rev_id + 0x1; in vi_common_early_init()
1680 adev->cg_flags = AMD_CG_SUPPORT_UVD_MGCG | in vi_common_early_init()
1694 adev->pg_flags = AMD_PG_SUPPORT_GFX_PG | in vi_common_early_init()
1700 adev->external_rev_id = adev->rev_id + 0x61; in vi_common_early_init()
1707 if (amdgpu_sriov_vf(adev)) { in vi_common_early_init()
1708 amdgpu_virt_init_setting(adev); in vi_common_early_init()
1709 xgpu_vi_mailbox_set_irq_funcs(adev); in vi_common_early_init()
1717 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in vi_common_late_init() local
1719 if (amdgpu_sriov_vf(adev)) in vi_common_late_init()
1720 xgpu_vi_mailbox_get_irq(adev); in vi_common_late_init()
1727 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in vi_common_sw_init() local
1729 if (amdgpu_sriov_vf(adev)) in vi_common_sw_init()
1730 xgpu_vi_mailbox_add_irq_id(adev); in vi_common_sw_init()
1742 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in vi_common_hw_init() local
1745 vi_init_golden_registers(adev); in vi_common_hw_init()
1747 vi_pcie_gen3_enable(adev); in vi_common_hw_init()
1749 vi_program_aspm(adev); in vi_common_hw_init()
1751 vi_enable_doorbell_aperture(adev, true); in vi_common_hw_init()
1758 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in vi_common_hw_fini() local
1761 vi_enable_doorbell_aperture(adev, false); in vi_common_hw_fini()
1763 if (amdgpu_sriov_vf(adev)) in vi_common_hw_fini()
1764 xgpu_vi_mailbox_put_irq(adev); in vi_common_hw_fini()
1771 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in vi_common_suspend() local
1773 return vi_common_hw_fini(adev); in vi_common_suspend()
1778 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in vi_common_resume() local
1780 return vi_common_hw_init(adev); in vi_common_resume()
1798 static void vi_update_bif_medium_grain_light_sleep(struct amdgpu_device *adev, in vi_update_bif_medium_grain_light_sleep() argument
1805 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) in vi_update_bif_medium_grain_light_sleep()
1818 static void vi_update_hdp_medium_grain_clock_gating(struct amdgpu_device *adev, in vi_update_hdp_medium_grain_clock_gating() argument
1825 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG)) in vi_update_hdp_medium_grain_clock_gating()
1834 static void vi_update_hdp_light_sleep(struct amdgpu_device *adev, in vi_update_hdp_light_sleep() argument
1841 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS)) in vi_update_hdp_light_sleep()
1850 static void vi_update_drm_light_sleep(struct amdgpu_device *adev, in vi_update_drm_light_sleep() argument
1857 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS)) in vi_update_drm_light_sleep()
1867 static void vi_update_rom_medium_grain_clock_gating(struct amdgpu_device *adev, in vi_update_rom_medium_grain_clock_gating() argument
1874 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG)) in vi_update_rom_medium_grain_clock_gating()
1890 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in vi_common_set_clockgating_state_by_smu() local
1892 if (adev->cg_flags & (AMD_CG_SUPPORT_MC_LS | AMD_CG_SUPPORT_MC_MGCG)) { in vi_common_set_clockgating_state_by_smu()
1893 if (adev->cg_flags & AMD_CG_SUPPORT_MC_LS) { in vi_common_set_clockgating_state_by_smu()
1897 if (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG) { in vi_common_set_clockgating_state_by_smu()
1907 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id); in vi_common_set_clockgating_state_by_smu()
1910 if (adev->cg_flags & (AMD_CG_SUPPORT_SDMA_LS | AMD_CG_SUPPORT_SDMA_MGCG)) { in vi_common_set_clockgating_state_by_smu()
1911 if (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS) { in vi_common_set_clockgating_state_by_smu()
1915 if (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG) { in vi_common_set_clockgating_state_by_smu()
1925 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id); in vi_common_set_clockgating_state_by_smu()
1928 if (adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS | AMD_CG_SUPPORT_HDP_MGCG)) { in vi_common_set_clockgating_state_by_smu()
1929 if (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS) { in vi_common_set_clockgating_state_by_smu()
1933 if (adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG) { in vi_common_set_clockgating_state_by_smu()
1943 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id); in vi_common_set_clockgating_state_by_smu()
1947 if (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS) { in vi_common_set_clockgating_state_by_smu()
1957 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id); in vi_common_set_clockgating_state_by_smu()
1959 if (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG) { in vi_common_set_clockgating_state_by_smu()
1969 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id); in vi_common_set_clockgating_state_by_smu()
1972 if (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS) { in vi_common_set_clockgating_state_by_smu()
1983 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id); in vi_common_set_clockgating_state_by_smu()
1986 if (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG) { in vi_common_set_clockgating_state_by_smu()
1997 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id); in vi_common_set_clockgating_state_by_smu()
2005 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in vi_common_set_clockgating_state() local
2007 if (amdgpu_sriov_vf(adev)) in vi_common_set_clockgating_state()
2010 switch (adev->asic_type) { in vi_common_set_clockgating_state()
2012 vi_update_bif_medium_grain_light_sleep(adev, in vi_common_set_clockgating_state()
2014 vi_update_hdp_medium_grain_clock_gating(adev, in vi_common_set_clockgating_state()
2016 vi_update_hdp_light_sleep(adev, in vi_common_set_clockgating_state()
2018 vi_update_rom_medium_grain_clock_gating(adev, in vi_common_set_clockgating_state()
2023 vi_update_bif_medium_grain_light_sleep(adev, in vi_common_set_clockgating_state()
2025 vi_update_hdp_medium_grain_clock_gating(adev, in vi_common_set_clockgating_state()
2027 vi_update_hdp_light_sleep(adev, in vi_common_set_clockgating_state()
2029 vi_update_drm_light_sleep(adev, in vi_common_set_clockgating_state()
2037 vi_common_set_clockgating_state_by_smu(adev, state); in vi_common_set_clockgating_state()
2053 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in vi_common_get_clockgating_state() local
2056 if (amdgpu_sriov_vf(adev)) in vi_common_get_clockgating_state()
2107 void vi_set_virt_ops(struct amdgpu_device *adev) in vi_set_virt_ops() argument
2109 adev->virt.ops = &xgpu_vi_virt_ops; in vi_set_virt_ops()
2112 int vi_set_ip_blocks(struct amdgpu_device *adev) in vi_set_ip_blocks() argument
2114 switch (adev->asic_type) { in vi_set_ip_blocks()
2117 amdgpu_device_ip_block_add(adev, &vi_common_ip_block); in vi_set_ip_blocks()
2118 amdgpu_device_ip_block_add(adev, &gmc_v7_4_ip_block); in vi_set_ip_blocks()
2119 amdgpu_device_ip_block_add(adev, &iceland_ih_ip_block); in vi_set_ip_blocks()
2120 amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block); in vi_set_ip_blocks()
2121 amdgpu_device_ip_block_add(adev, &sdma_v2_4_ip_block); in vi_set_ip_blocks()
2122 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block); in vi_set_ip_blocks()
2123 if (adev->enable_virtual_display) in vi_set_ip_blocks()
2124 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); in vi_set_ip_blocks()
2127 amdgpu_device_ip_block_add(adev, &vi_common_ip_block); in vi_set_ip_blocks()
2128 amdgpu_device_ip_block_add(adev, &gmc_v8_5_ip_block); in vi_set_ip_blocks()
2129 amdgpu_device_ip_block_add(adev, &tonga_ih_ip_block); in vi_set_ip_blocks()
2130 amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block); in vi_set_ip_blocks()
2131 amdgpu_device_ip_block_add(adev, &sdma_v3_0_ip_block); in vi_set_ip_blocks()
2132 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block); in vi_set_ip_blocks()
2133 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) in vi_set_ip_blocks()
2134 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); in vi_set_ip_blocks()
2136 else if (amdgpu_device_has_dc_support(adev)) in vi_set_ip_blocks()
2137 amdgpu_device_ip_block_add(adev, &dm_ip_block); in vi_set_ip_blocks()
2140 amdgpu_device_ip_block_add(adev, &dce_v10_1_ip_block); in vi_set_ip_blocks()
2141 if (!amdgpu_sriov_vf(adev)) { in vi_set_ip_blocks()
2142 amdgpu_device_ip_block_add(adev, &uvd_v6_0_ip_block); in vi_set_ip_blocks()
2143 amdgpu_device_ip_block_add(adev, &vce_v3_0_ip_block); in vi_set_ip_blocks()
2147 amdgpu_device_ip_block_add(adev, &vi_common_ip_block); in vi_set_ip_blocks()
2148 amdgpu_device_ip_block_add(adev, &gmc_v8_0_ip_block); in vi_set_ip_blocks()
2149 amdgpu_device_ip_block_add(adev, &tonga_ih_ip_block); in vi_set_ip_blocks()
2150 amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block); in vi_set_ip_blocks()
2151 amdgpu_device_ip_block_add(adev, &sdma_v3_0_ip_block); in vi_set_ip_blocks()
2152 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block); in vi_set_ip_blocks()
2153 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) in vi_set_ip_blocks()
2154 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); in vi_set_ip_blocks()
2156 else if (amdgpu_device_has_dc_support(adev)) in vi_set_ip_blocks()
2157 amdgpu_device_ip_block_add(adev, &dm_ip_block); in vi_set_ip_blocks()
2160 amdgpu_device_ip_block_add(adev, &dce_v10_0_ip_block); in vi_set_ip_blocks()
2161 if (!amdgpu_sriov_vf(adev)) { in vi_set_ip_blocks()
2162 amdgpu_device_ip_block_add(adev, &uvd_v5_0_ip_block); in vi_set_ip_blocks()
2163 amdgpu_device_ip_block_add(adev, &vce_v3_0_ip_block); in vi_set_ip_blocks()
2170 amdgpu_device_ip_block_add(adev, &vi_common_ip_block); in vi_set_ip_blocks()
2171 amdgpu_device_ip_block_add(adev, &gmc_v8_1_ip_block); in vi_set_ip_blocks()
2172 amdgpu_device_ip_block_add(adev, &tonga_ih_ip_block); in vi_set_ip_blocks()
2173 amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block); in vi_set_ip_blocks()
2174 amdgpu_device_ip_block_add(adev, &sdma_v3_1_ip_block); in vi_set_ip_blocks()
2175 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block); in vi_set_ip_blocks()
2176 if (adev->enable_virtual_display) in vi_set_ip_blocks()
2177 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); in vi_set_ip_blocks()
2179 else if (amdgpu_device_has_dc_support(adev)) in vi_set_ip_blocks()
2180 amdgpu_device_ip_block_add(adev, &dm_ip_block); in vi_set_ip_blocks()
2183 amdgpu_device_ip_block_add(adev, &dce_v11_2_ip_block); in vi_set_ip_blocks()
2184 amdgpu_device_ip_block_add(adev, &uvd_v6_3_ip_block); in vi_set_ip_blocks()
2185 amdgpu_device_ip_block_add(adev, &vce_v3_4_ip_block); in vi_set_ip_blocks()
2188 amdgpu_device_ip_block_add(adev, &vi_common_ip_block); in vi_set_ip_blocks()
2189 amdgpu_device_ip_block_add(adev, &gmc_v8_0_ip_block); in vi_set_ip_blocks()
2190 amdgpu_device_ip_block_add(adev, &cz_ih_ip_block); in vi_set_ip_blocks()
2191 amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block); in vi_set_ip_blocks()
2192 amdgpu_device_ip_block_add(adev, &sdma_v3_0_ip_block); in vi_set_ip_blocks()
2193 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block); in vi_set_ip_blocks()
2194 if (adev->enable_virtual_display) in vi_set_ip_blocks()
2195 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); in vi_set_ip_blocks()
2197 else if (amdgpu_device_has_dc_support(adev)) in vi_set_ip_blocks()
2198 amdgpu_device_ip_block_add(adev, &dm_ip_block); in vi_set_ip_blocks()
2201 amdgpu_device_ip_block_add(adev, &dce_v11_0_ip_block); in vi_set_ip_blocks()
2202 amdgpu_device_ip_block_add(adev, &uvd_v6_0_ip_block); in vi_set_ip_blocks()
2203 amdgpu_device_ip_block_add(adev, &vce_v3_1_ip_block); in vi_set_ip_blocks()
2205 amdgpu_device_ip_block_add(adev, &acp_ip_block); in vi_set_ip_blocks()
2209 amdgpu_device_ip_block_add(adev, &vi_common_ip_block); in vi_set_ip_blocks()
2210 amdgpu_device_ip_block_add(adev, &gmc_v8_0_ip_block); in vi_set_ip_blocks()
2211 amdgpu_device_ip_block_add(adev, &cz_ih_ip_block); in vi_set_ip_blocks()
2212 amdgpu_device_ip_block_add(adev, &gfx_v8_1_ip_block); in vi_set_ip_blocks()
2213 amdgpu_device_ip_block_add(adev, &sdma_v3_0_ip_block); in vi_set_ip_blocks()
2214 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block); in vi_set_ip_blocks()
2215 if (adev->enable_virtual_display) in vi_set_ip_blocks()
2216 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); in vi_set_ip_blocks()
2218 else if (amdgpu_device_has_dc_support(adev)) in vi_set_ip_blocks()
2219 amdgpu_device_ip_block_add(adev, &dm_ip_block); in vi_set_ip_blocks()
2222 amdgpu_device_ip_block_add(adev, &dce_v11_0_ip_block); in vi_set_ip_blocks()
2223 amdgpu_device_ip_block_add(adev, &uvd_v6_2_ip_block); in vi_set_ip_blocks()
2224 amdgpu_device_ip_block_add(adev, &vce_v3_4_ip_block); in vi_set_ip_blocks()
2226 amdgpu_device_ip_block_add(adev, &acp_ip_block); in vi_set_ip_blocks()
2237 void legacy_doorbell_index_init(struct amdgpu_device *adev) in legacy_doorbell_index_init() argument
2239 adev->doorbell_index.kiq = AMDGPU_DOORBELL_KIQ; in legacy_doorbell_index_init()
2240 adev->doorbell_index.mec_ring0 = AMDGPU_DOORBELL_MEC_RING0; in legacy_doorbell_index_init()
2241 adev->doorbell_index.mec_ring1 = AMDGPU_DOORBELL_MEC_RING1; in legacy_doorbell_index_init()
2242 adev->doorbell_index.mec_ring2 = AMDGPU_DOORBELL_MEC_RING2; in legacy_doorbell_index_init()
2243 adev->doorbell_index.mec_ring3 = AMDGPU_DOORBELL_MEC_RING3; in legacy_doorbell_index_init()
2244 adev->doorbell_index.mec_ring4 = AMDGPU_DOORBELL_MEC_RING4; in legacy_doorbell_index_init()
2245 adev->doorbell_index.mec_ring5 = AMDGPU_DOORBELL_MEC_RING5; in legacy_doorbell_index_init()
2246 adev->doorbell_index.mec_ring6 = AMDGPU_DOORBELL_MEC_RING6; in legacy_doorbell_index_init()
2247 adev->doorbell_index.mec_ring7 = AMDGPU_DOORBELL_MEC_RING7; in legacy_doorbell_index_init()
2248 adev->doorbell_index.gfx_ring0 = AMDGPU_DOORBELL_GFX_RING0; in legacy_doorbell_index_init()
2249 adev->doorbell_index.sdma_engine[0] = AMDGPU_DOORBELL_sDMA_ENGINE0; in legacy_doorbell_index_init()
2250 adev->doorbell_index.sdma_engine[1] = AMDGPU_DOORBELL_sDMA_ENGINE1; in legacy_doorbell_index_init()
2251 adev->doorbell_index.ih = AMDGPU_DOORBELL_IH; in legacy_doorbell_index_init()
2252 adev->doorbell_index.max_assignment = AMDGPU_DOORBELL_MAX_ASSIGNMENT; in legacy_doorbell_index_init()