Lines Matching refs:VCN
166 adev->vcn.inst[i].external.scratch9 = SOC15_REG_OFFSET(VCN, i, mmUVD_SCRATCH9); in vcn_v3_0_sw_init()
168 adev->vcn.inst[i].external.data0 = SOC15_REG_OFFSET(VCN, i, mmUVD_GPCOM_VCPU_DATA0); in vcn_v3_0_sw_init()
170 adev->vcn.inst[i].external.data1 = SOC15_REG_OFFSET(VCN, i, mmUVD_GPCOM_VCPU_DATA1); in vcn_v3_0_sw_init()
172 adev->vcn.inst[i].external.cmd = SOC15_REG_OFFSET(VCN, i, mmUVD_GPCOM_VCPU_CMD); in vcn_v3_0_sw_init()
174 adev->vcn.inst[i].external.nop = SOC15_REG_OFFSET(VCN, i, mmUVD_NO_OP); in vcn_v3_0_sw_init()
386 RREG32_SOC15(VCN, i, mmUVD_STATUS))) { in vcn_v3_0_hw_fini()
452 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, in vcn_v3_0_mc_resume()
454 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, in vcn_v3_0_mc_resume()
456 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET0, 0); in vcn_v3_0_mc_resume()
459 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, in vcn_v3_0_mc_resume()
461 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, in vcn_v3_0_mc_resume()
464 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET0, in vcn_v3_0_mc_resume()
467 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_SIZE0, size); in vcn_v3_0_mc_resume()
470 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, in vcn_v3_0_mc_resume()
472 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, in vcn_v3_0_mc_resume()
474 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET1, 0); in vcn_v3_0_mc_resume()
475 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE); in vcn_v3_0_mc_resume()
478 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, in vcn_v3_0_mc_resume()
480 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, in vcn_v3_0_mc_resume()
482 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET2, 0); in vcn_v3_0_mc_resume()
483 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE); in vcn_v3_0_mc_resume()
486 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW, in vcn_v3_0_mc_resume()
488 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH, in vcn_v3_0_mc_resume()
490 WREG32_SOC15(VCN, inst, mmUVD_VCPU_NONCACHE_OFFSET0, 0); in vcn_v3_0_mc_resume()
491 WREG32_SOC15(VCN, inst, mmUVD_VCPU_NONCACHE_SIZE0, in vcn_v3_0_mc_resume()
504 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), in vcn_v3_0_mc_resume_dpg_mode()
507 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), in vcn_v3_0_mc_resume_dpg_mode()
510 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
513 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
515 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
517 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
522 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), in vcn_v3_0_mc_resume_dpg_mode()
525 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), in vcn_v3_0_mc_resume_dpg_mode()
529 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET0), in vcn_v3_0_mc_resume_dpg_mode()
535 VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE0), size, 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
538 VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE0), 0, 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
543 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), in vcn_v3_0_mc_resume_dpg_mode()
546 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), in vcn_v3_0_mc_resume_dpg_mode()
549 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
552 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
554 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
556 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
559 VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
563 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), in vcn_v3_0_mc_resume_dpg_mode()
566 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), in vcn_v3_0_mc_resume_dpg_mode()
569 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
571 VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
575 VCN, inst_idx, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), in vcn_v3_0_mc_resume_dpg_mode()
578 VCN, inst_idx, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), in vcn_v3_0_mc_resume_dpg_mode()
581 VCN, inst_idx, mmUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
583 VCN, inst_idx, mmUVD_VCPU_NONCACHE_SIZE0), in vcn_v3_0_mc_resume_dpg_mode()
611 WREG32_SOC15(VCN, inst, mmUVD_PGFSM_CONFIG, data); in vcn_v3_0_disable_static_power_gating()
612 SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_PGFSM_STATUS, in vcn_v3_0_disable_static_power_gating()
629 WREG32_SOC15(VCN, inst, mmUVD_PGFSM_CONFIG, data); in vcn_v3_0_disable_static_power_gating()
630 SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_PGFSM_STATUS, 0, 0x3F3FFFFF); in vcn_v3_0_disable_static_power_gating()
633 data = RREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS); in vcn_v3_0_disable_static_power_gating()
639 WREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS, data); in vcn_v3_0_disable_static_power_gating()
648 data = RREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS); in vcn_v3_0_enable_static_power_gating()
651 WREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS, data); in vcn_v3_0_enable_static_power_gating()
667 WREG32_SOC15(VCN, inst, mmUVD_PGFSM_CONFIG, data); in vcn_v3_0_enable_static_power_gating()
683 SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_PGFSM_STATUS, data, 0x3F3FFFFF); in vcn_v3_0_enable_static_power_gating()
700 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL); in vcn_v3_0_disable_clock_gating()
707 WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data); in vcn_v3_0_disable_clock_gating()
709 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_GATE); in vcn_v3_0_disable_clock_gating()
731 WREG32_SOC15(VCN, inst, mmUVD_CGC_GATE, data); in vcn_v3_0_disable_clock_gating()
733 SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_CGC_GATE, 0, 0xFFFFFFFF); in vcn_v3_0_disable_clock_gating()
735 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL); in vcn_v3_0_disable_clock_gating()
756 WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data); in vcn_v3_0_disable_clock_gating()
758 data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE); in vcn_v3_0_disable_clock_gating()
790 WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE, data); in vcn_v3_0_disable_clock_gating()
792 data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE2); in vcn_v3_0_disable_clock_gating()
798 WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE2, data); in vcn_v3_0_disable_clock_gating()
800 data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL); in vcn_v3_0_disable_clock_gating()
820 WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL, data); in vcn_v3_0_disable_clock_gating()
856 VCN, inst_idx, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect); in vcn_v3_0_clock_gating_dpg_mode()
860 VCN, inst_idx, mmUVD_CGC_GATE), 0, sram_sel, indirect); in vcn_v3_0_clock_gating_dpg_mode()
864 VCN, inst_idx, mmUVD_SUVD_CGC_GATE), 1, sram_sel, indirect); in vcn_v3_0_clock_gating_dpg_mode()
868 VCN, inst_idx, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect); in vcn_v3_0_clock_gating_dpg_mode()
884 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL); in vcn_v3_0_enable_clock_gating()
891 WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data); in vcn_v3_0_enable_clock_gating()
893 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL); in vcn_v3_0_enable_clock_gating()
914 WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data); in vcn_v3_0_enable_clock_gating()
916 data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL); in vcn_v3_0_enable_clock_gating()
936 WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL, data); in vcn_v3_0_enable_clock_gating()
946 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1, in vcn_v3_0_start_dpg_mode()
949 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_POWER_STATUS); in vcn_v3_0_start_dpg_mode()
952 WREG32_SOC15(VCN, inst_idx, mmUVD_POWER_STATUS, tmp); in vcn_v3_0_start_dpg_mode()
965 VCN, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect); in vcn_v3_0_start_dpg_mode()
969 VCN, inst_idx, mmUVD_MASTINT_EN), 0, 0, indirect); in vcn_v3_0_start_dpg_mode()
981 VCN, inst_idx, mmUVD_LMI_CTRL), tmp, 0, indirect); in vcn_v3_0_start_dpg_mode()
984 VCN, inst_idx, mmUVD_MPC_CNTL), in vcn_v3_0_start_dpg_mode()
988 VCN, inst_idx, mmUVD_MPC_SET_MUXA0), in vcn_v3_0_start_dpg_mode()
995 VCN, inst_idx, mmUVD_MPC_SET_MUXB0), in vcn_v3_0_start_dpg_mode()
1002 VCN, inst_idx, mmUVD_MPC_SET_MUX), in vcn_v3_0_start_dpg_mode()
1010 VCN, inst_idx, mmUVD_REG_XX_MASK), 0x10, 0, indirect); in vcn_v3_0_start_dpg_mode()
1012 VCN, inst_idx, mmUVD_RBC_XX_IB_REG_CHECK), 0x3, 0, indirect); in vcn_v3_0_start_dpg_mode()
1016 VCN, inst_idx, mmUVD_LMI_CTRL2), 0, 0, indirect); in vcn_v3_0_start_dpg_mode()
1020 VCN, inst_idx, mmUVD_RB_ARB_CTRL), 0, 0, indirect); in vcn_v3_0_start_dpg_mode()
1025 VCN, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect); in vcn_v3_0_start_dpg_mode()
1029 VCN, inst_idx, mmUVD_MASTINT_EN), in vcn_v3_0_start_dpg_mode()
1034 VCN, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect); in vcn_v3_0_start_dpg_mode()
1049 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_CNTL, tmp); in vcn_v3_0_start_dpg_mode()
1052 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), in vcn_v3_0_start_dpg_mode()
1058 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR_CNTL, 0); in vcn_v3_0_start_dpg_mode()
1061 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR_ADDR, in vcn_v3_0_start_dpg_mode()
1065 WREG32_SOC15(VCN, inst_idx, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, in vcn_v3_0_start_dpg_mode()
1067 WREG32_SOC15(VCN, inst_idx, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, in vcn_v3_0_start_dpg_mode()
1071 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR, 0); in vcn_v3_0_start_dpg_mode()
1073 WREG32_SOC15(VCN, inst_idx, mmUVD_SCRATCH2, 0); in vcn_v3_0_start_dpg_mode()
1075 ring->wptr = RREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR); in vcn_v3_0_start_dpg_mode()
1076 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR, in vcn_v3_0_start_dpg_mode()
1087 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), in vcn_v3_0_start_dpg_mode()
1116 tmp = RREG32_SOC15(VCN, i, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY; in vcn_v3_0_start()
1117 WREG32_SOC15(VCN, i, mmUVD_STATUS, tmp); in vcn_v3_0_start()
1123 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), in vcn_v3_0_start()
1127 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN), 0, in vcn_v3_0_start()
1131 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_LMI_CTRL2), 0, in vcn_v3_0_start()
1134 tmp = RREG32_SOC15(VCN, i, mmUVD_SOFT_RESET); in vcn_v3_0_start()
1137 WREG32_SOC15(VCN, i, mmUVD_SOFT_RESET, tmp); in vcn_v3_0_start()
1140 tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL); in vcn_v3_0_start()
1141 WREG32_SOC15(VCN, i, mmUVD_LMI_CTRL, tmp | in vcn_v3_0_start()
1148 tmp = RREG32_SOC15(VCN, i, mmUVD_MPC_CNTL); in vcn_v3_0_start()
1151 WREG32_SOC15(VCN, i, mmUVD_MPC_CNTL, tmp); in vcn_v3_0_start()
1154 WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUXA0, in vcn_v3_0_start()
1161 WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUXB0, in vcn_v3_0_start()
1168 WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUX, in vcn_v3_0_start()
1176 WREG32_SOC15(VCN, i, mmUVD_GFX10_ADDR_CONFIG, in vcn_v3_0_start()
1180 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_RB_ARB_CTRL), 0, in vcn_v3_0_start()
1184 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0, in vcn_v3_0_start()
1191 status = RREG32_SOC15(VCN, i, mmUVD_STATUS); in vcn_v3_0_start()
1201 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), in vcn_v3_0_start()
1205 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0, in vcn_v3_0_start()
1218 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN), in vcn_v3_0_start()
1223 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_STATUS), 0, in vcn_v3_0_start()
1226 WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_VMID, 0); in vcn_v3_0_start()
1236 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_CNTL, tmp); in vcn_v3_0_start()
1242 WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, in vcn_v3_0_start()
1244 WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, in vcn_v3_0_start()
1248 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR, 0); in vcn_v3_0_start()
1250 WREG32_SOC15(VCN, i, mmUVD_SCRATCH2, 0); in vcn_v3_0_start()
1251 ring->wptr = RREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR); in vcn_v3_0_start()
1252 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_WPTR, in vcn_v3_0_start()
1260 WREG32_SOC15(VCN, i, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); in vcn_v3_0_start()
1261 WREG32_SOC15(VCN, i, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); in vcn_v3_0_start()
1262 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO, ring->gpu_addr); in vcn_v3_0_start()
1263 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); in vcn_v3_0_start()
1264 WREG32_SOC15(VCN, i, mmUVD_RB_SIZE, ring->ring_size / 4); in vcn_v3_0_start()
1269 WREG32_SOC15(VCN, i, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); in vcn_v3_0_start()
1270 WREG32_SOC15(VCN, i, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); in vcn_v3_0_start()
1271 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO2, ring->gpu_addr); in vcn_v3_0_start()
1272 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); in vcn_v3_0_start()
1273 WREG32_SOC15(VCN, i, mmUVD_RB_SIZE2, ring->ring_size / 4); in vcn_v3_0_start()
1327 MMSCH_V3_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCN, i, in vcn_v3_0_start_sriov()
1334 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, in vcn_v3_0_start_sriov()
1337 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, in vcn_v3_0_start_sriov()
1341 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, in vcn_v3_0_start_sriov()
1345 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, in vcn_v3_0_start_sriov()
1348 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, in vcn_v3_0_start_sriov()
1352 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, in vcn_v3_0_start_sriov()
1357 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, in vcn_v3_0_start_sriov()
1362 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, in vcn_v3_0_start_sriov()
1365 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, in vcn_v3_0_start_sriov()
1368 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, in vcn_v3_0_start_sriov()
1371 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, in vcn_v3_0_start_sriov()
1377 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, in vcn_v3_0_start_sriov()
1380 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, in vcn_v3_0_start_sriov()
1383 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, in vcn_v3_0_start_sriov()
1386 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, in vcn_v3_0_start_sriov()
1394 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, in vcn_v3_0_start_sriov()
1397 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, in vcn_v3_0_start_sriov()
1400 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, in vcn_v3_0_start_sriov()
1408 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, in vcn_v3_0_start_sriov()
1411 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, in vcn_v3_0_start_sriov()
1421 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, in vcn_v3_0_start_sriov()
1445 WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_ADDR_LO, lower_32_bits(ctx_addr)); in vcn_v3_0_start_sriov()
1446 WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_ADDR_HI, upper_32_bits(ctx_addr)); in vcn_v3_0_start_sriov()
1449 tmp = RREG32_SOC15(VCN, 0, mmMMSCH_VF_VMID); in vcn_v3_0_start_sriov()
1453 WREG32_SOC15(VCN, 0, mmMMSCH_VF_VMID, tmp); in vcn_v3_0_start_sriov()
1457 WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_SIZE, size); in vcn_v3_0_start_sriov()
1460 WREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_RESP, 0); in vcn_v3_0_start_sriov()
1466 WREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_HOST, param); in vcn_v3_0_start_sriov()
1472 resp = RREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_RESP); in vcn_v3_0_start_sriov()
1498 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1, in vcn_v3_0_stop_dpg_mode()
1502 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR); in vcn_v3_0_stop_dpg_mode()
1503 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF); in vcn_v3_0_stop_dpg_mode()
1505 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR2); in vcn_v3_0_stop_dpg_mode()
1506 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF); in vcn_v3_0_stop_dpg_mode()
1508 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF; in vcn_v3_0_stop_dpg_mode()
1509 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF); in vcn_v3_0_stop_dpg_mode()
1511 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1, in vcn_v3_0_stop_dpg_mode()
1515 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 0, in vcn_v3_0_stop_dpg_mode()
1536 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7); in vcn_v3_0_stop()
1544 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp); in vcn_v3_0_stop()
1549 tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2); in vcn_v3_0_stop()
1551 WREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2, tmp); in vcn_v3_0_stop()
1554 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp); in vcn_v3_0_stop()
1559 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_RB_ARB_CTRL), in vcn_v3_0_stop()
1564 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), in vcn_v3_0_stop()
1569 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0, in vcn_v3_0_stop()
1573 tmp = RREG32_SOC15(VCN, i, mmUVD_SOFT_RESET); in vcn_v3_0_stop()
1575 WREG32_SOC15(VCN, i, mmUVD_SOFT_RESET, tmp); in vcn_v3_0_stop()
1576 tmp = RREG32_SOC15(VCN, i, mmUVD_SOFT_RESET); in vcn_v3_0_stop()
1578 WREG32_SOC15(VCN, i, mmUVD_SOFT_RESET, tmp); in vcn_v3_0_stop()
1581 WREG32_SOC15(VCN, i, mmUVD_STATUS, 0); in vcn_v3_0_stop()
1608 reg_data = RREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE) & in vcn_v3_0_pause_dpg_mode()
1612 ret_code = SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 0x1, in vcn_v3_0_pause_dpg_mode()
1618 WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE, reg_data); in vcn_v3_0_pause_dpg_mode()
1621 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_DPG_PAUSE, in vcn_v3_0_pause_dpg_mode()
1626 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), in vcn_v3_0_pause_dpg_mode()
1636 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_LO, ring->gpu_addr); in vcn_v3_0_pause_dpg_mode()
1637 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); in vcn_v3_0_pause_dpg_mode()
1638 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_SIZE, ring->ring_size / 4); in vcn_v3_0_pause_dpg_mode()
1639 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); in vcn_v3_0_pause_dpg_mode()
1640 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); in vcn_v3_0_pause_dpg_mode()
1646 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_LO2, ring->gpu_addr); in vcn_v3_0_pause_dpg_mode()
1647 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); in vcn_v3_0_pause_dpg_mode()
1648 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_SIZE2, ring->ring_size / 4); in vcn_v3_0_pause_dpg_mode()
1649 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); in vcn_v3_0_pause_dpg_mode()
1650 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); in vcn_v3_0_pause_dpg_mode()
1654 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR, fw_shared->rb.rptr); in vcn_v3_0_pause_dpg_mode()
1655 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR, fw_shared->rb.wptr); in vcn_v3_0_pause_dpg_mode()
1659 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), in vcn_v3_0_pause_dpg_mode()
1662 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, in vcn_v3_0_pause_dpg_mode()
1668 WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE, reg_data); in vcn_v3_0_pause_dpg_mode()
1687 return RREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_RPTR); in vcn_v3_0_dec_ring_get_rptr()
1704 return RREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_WPTR); in vcn_v3_0_dec_ring_get_wptr()
1723 WREG32_SOC15(VCN, ring->me, mmUVD_SCRATCH2, in vcn_v3_0_dec_ring_set_wptr()
1731 WREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); in vcn_v3_0_dec_ring_set_wptr()
1937 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_RPTR); in vcn_v3_0_enc_ring_get_rptr()
1939 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_RPTR2); in vcn_v3_0_enc_ring_get_rptr()
1957 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR); in vcn_v3_0_enc_ring_get_wptr()
1962 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR2); in vcn_v3_0_enc_ring_get_wptr()
1982 WREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); in vcn_v3_0_enc_ring_set_wptr()
1989 WREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); in vcn_v3_0_enc_ring_set_wptr()
2068 ret &= (RREG32_SOC15(VCN, i, mmUVD_STATUS) == UVD_STATUS__IDLE); in vcn_v3_0_is_idle()
2083 ret = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, in vcn_v3_0_wait_for_idle()
2104 if (RREG32_SOC15(VCN, i, mmUVD_STATUS) != UVD_STATUS__IDLE) in vcn_v3_0_set_clockgating_state()