85 		adev->vcn.num_vcn_inst = 2;  in vcn_v2_5_early_init()
86 		adev->vcn.harvest_config = 0;  in vcn_v2_5_early_init()
87 		adev->vcn.num_enc_rings = 1;  in vcn_v2_5_early_init()
92 		for (i = 0; i < adev->vcn.num_vcn_inst; i++) {  in vcn_v2_5_early_init()
95 				adev->vcn.harvest_config |= 1 << i;  in vcn_v2_5_early_init()
97 		if (adev->vcn.harvest_config == (AMDGPU_VCN_HARVEST_VCN0 |  in vcn_v2_5_early_init()
102 		adev->vcn.num_enc_rings = 2;  in vcn_v2_5_early_init()
126 	for (j = 0; j < adev->vcn.num_vcn_inst; j++) {  in vcn_v2_5_sw_init()
127 		if (adev->vcn.harvest_config & (1 << j))  in vcn_v2_5_sw_init()
131 				VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, &adev->vcn.inst[j].irq);  in vcn_v2_5_sw_init()
136 		for (i = 0; i < adev->vcn.num_enc_rings; ++i) {  in vcn_v2_5_sw_init()
138 				i + VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst[j].irq);  in vcn_v2_5_sw_init()
145 			VCN_2_6__SRCID_UVD_POISON, &adev->vcn.inst[j].irq);  in vcn_v2_5_sw_init()
160 	for (j = 0; j < adev->vcn.num_vcn_inst; j++) {  in vcn_v2_5_sw_init()
163 		if (adev->vcn.harvest_config & (1 << j))  in vcn_v2_5_sw_init()
165 		adev->vcn.internal.context_id = mmUVD_CONTEXT_ID_INTERNAL_OFFSET;  in vcn_v2_5_sw_init()
166 		adev->vcn.internal.ib_vmid = mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET;  in vcn_v2_5_sw_init()
167 		adev->vcn.internal.ib_bar_low = mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET;  in vcn_v2_5_sw_init()
168 		adev->vcn.internal.ib_bar_high = mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET;  in vcn_v2_5_sw_init()
169 		adev->vcn.internal.ib_size = mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET;  in vcn_v2_5_sw_init()
170 		adev->vcn.internal.gp_scratch8 = mmUVD_GP_SCRATCH8_INTERNAL_OFFSET;  in vcn_v2_5_sw_init()
172 		adev->vcn.internal.scratch9 = mmUVD_SCRATCH9_INTERNAL_OFFSET;  in vcn_v2_5_sw_init()
173 		adev->vcn.inst[j].external.scratch9 = SOC15_REG_OFFSET(VCN, j, mmUVD_SCRATCH9);  in vcn_v2_5_sw_init()
174 		adev->vcn.internal.data0 = mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET;  in vcn_v2_5_sw_init()
175 		adev->vcn.inst[j].external.data0 = SOC15_REG_OFFSET(VCN, j, mmUVD_GPCOM_VCPU_DATA0);  in vcn_v2_5_sw_init()
176 		adev->vcn.internal.data1 = mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET;  in vcn_v2_5_sw_init()
177 		adev->vcn.inst[j].external.data1 = SOC15_REG_OFFSET(VCN, j, mmUVD_GPCOM_VCPU_DATA1);  in vcn_v2_5_sw_init()
178 		adev->vcn.internal.cmd = mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET;  in vcn_v2_5_sw_init()
179 		adev->vcn.inst[j].external.cmd = SOC15_REG_OFFSET(VCN, j, mmUVD_GPCOM_VCPU_CMD);  in vcn_v2_5_sw_init()
180 		adev->vcn.internal.nop = mmUVD_NO_OP_INTERNAL_OFFSET;  in vcn_v2_5_sw_init()
181 		adev->vcn.inst[j].external.nop = SOC15_REG_OFFSET(VCN, j, mmUVD_NO_OP);  in vcn_v2_5_sw_init()
183 		ring = &adev->vcn.inst[j].ring_dec;  in vcn_v2_5_sw_init()
186 		ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) +  in vcn_v2_5_sw_init()
189 		r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[j].irq,  in vcn_v2_5_sw_init()
194 		for (i = 0; i < adev->vcn.num_enc_rings; ++i) {  in vcn_v2_5_sw_init()
197 			ring = &adev->vcn.inst[j].ring_enc[i];  in vcn_v2_5_sw_init()
200 			ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) +  in vcn_v2_5_sw_init()
205 					     &adev->vcn.inst[j].irq, 0,  in vcn_v2_5_sw_init()
211 		fw_shared = adev->vcn.inst[j].fw_shared.cpu_addr;  in vcn_v2_5_sw_init()
215 			amdgpu_vcn_fwlog_init(&adev->vcn.inst[i]);  in vcn_v2_5_sw_init()
225 		adev->vcn.pause_dpg_mode = vcn_v2_5_pause_dpg_mode;  in vcn_v2_5_sw_init()
244 		for (i = 0; i < adev->vcn.num_vcn_inst; i++) {  in vcn_v2_5_sw_fini()
245 			if (adev->vcn.harvest_config & (1 << i))  in vcn_v2_5_sw_fini()
247 			fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;  in vcn_v2_5_sw_fini()
282 	for (j = 0; j < adev->vcn.num_vcn_inst; ++j) {  in vcn_v2_5_hw_init()
283 		if (adev->vcn.harvest_config & (1 << j))  in vcn_v2_5_hw_init()
287 			adev->vcn.inst[j].ring_enc[0].sched.ready = true;  in vcn_v2_5_hw_init()
288 			adev->vcn.inst[j].ring_enc[1].sched.ready = false;  in vcn_v2_5_hw_init()
289 			adev->vcn.inst[j].ring_enc[2].sched.ready = false;  in vcn_v2_5_hw_init()
290 			adev->vcn.inst[j].ring_dec.sched.ready = true;  in vcn_v2_5_hw_init()
293 			ring = &adev->vcn.inst[j].ring_dec;  in vcn_v2_5_hw_init()
302 			for (i = 0; i < adev->vcn.num_enc_rings; ++i) {  in vcn_v2_5_hw_init()
303 				ring = &adev->vcn.inst[j].ring_enc[i];  in vcn_v2_5_hw_init()
331 	cancel_delayed_work_sync(&adev->vcn.idle_work);  in vcn_v2_5_hw_fini()
333 	for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {  in vcn_v2_5_hw_fini()
334 		if (adev->vcn.harvest_config & (1 << i))  in vcn_v2_5_hw_fini()
338 		    (adev->vcn.cur_state != AMD_PG_STATE_GATE &&  in vcn_v2_5_hw_fini()
397 	uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4);  in vcn_v2_5_mc_resume()
401 	for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {  in vcn_v2_5_mc_resume()
402 		if (adev->vcn.harvest_config & (1 << i))  in vcn_v2_5_mc_resume()
414 				lower_32_bits(adev->vcn.inst[i].gpu_addr));  in vcn_v2_5_mc_resume()
416 				upper_32_bits(adev->vcn.inst[i].gpu_addr));  in vcn_v2_5_mc_resume()
425 			lower_32_bits(adev->vcn.inst[i].gpu_addr + offset));  in vcn_v2_5_mc_resume()
427 			upper_32_bits(adev->vcn.inst[i].gpu_addr + offset));  in vcn_v2_5_mc_resume()
433 			lower_32_bits(adev->vcn.inst[i].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));  in vcn_v2_5_mc_resume()
435 			upper_32_bits(adev->vcn.inst[i].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));  in vcn_v2_5_mc_resume()
441 			lower_32_bits(adev->vcn.inst[i].fw_shared.gpu_addr));  in vcn_v2_5_mc_resume()
443 			upper_32_bits(adev->vcn.inst[i].fw_shared.gpu_addr));  in vcn_v2_5_mc_resume()
452 	uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4);  in vcn_v2_5_mc_resume_dpg_mode()
478 			lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);  in vcn_v2_5_mc_resume_dpg_mode()
481 			upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);  in vcn_v2_5_mc_resume_dpg_mode()
499 			lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);  in vcn_v2_5_mc_resume_dpg_mode()
502 			upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);  in vcn_v2_5_mc_resume_dpg_mode()
519 		lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);  in vcn_v2_5_mc_resume_dpg_mode()
522 		upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);  in vcn_v2_5_mc_resume_dpg_mode()
531 		lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect);  in vcn_v2_5_mc_resume_dpg_mode()
534 		upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect);  in vcn_v2_5_mc_resume_dpg_mode()
558 	for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {  in vcn_v2_5_disable_clock_gating()
559 		if (adev->vcn.harvest_config & (1 << i))  in vcn_v2_5_disable_clock_gating()
723 	for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {  in vcn_v2_5_enable_clock_gating()
724 		if (adev->vcn.harvest_config & (1 << i))  in vcn_v2_5_enable_clock_gating()
775 	volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr;  in vcn_v2_5_start_dpg_mode()
789 …adev->vcn.inst[inst_idx].dpg_sram_curr_addr = (uint32_t *)adev->vcn.inst[inst_idx].dpg_sram_cpu_ad…  in vcn_v2_5_start_dpg_mode()
867 		psp_update_vcn_sram(adev, inst_idx, adev->vcn.inst[inst_idx].dpg_sram_gpu_addr,  in vcn_v2_5_start_dpg_mode()
868 				    (uint32_t)((uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_curr_addr -  in vcn_v2_5_start_dpg_mode()
869 					       (uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr));  in vcn_v2_5_start_dpg_mode()
871 	ring = &adev->vcn.inst[inst_idx].ring_dec;  in vcn_v2_5_start_dpg_mode()
926 	for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {  in vcn_v2_5_start()
927 		if (adev->vcn.harvest_config & (1 << i))  in vcn_v2_5_start()
930 			r = vcn_v2_5_start_dpg_mode(adev, i, adev->vcn.indirect_sram);  in vcn_v2_5_start()
949 	for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {  in vcn_v2_5_start()
950 		if (adev->vcn.harvest_config & (1 << i))  in vcn_v2_5_start()
998 	for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {  in vcn_v2_5_start()
999 		volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;  in vcn_v2_5_start()
1000 		if (adev->vcn.harvest_config & (1 << i))  in vcn_v2_5_start()
1063 		ring = &adev->vcn.inst[i].ring_dec;  in vcn_v2_5_start()
1089 		ring = &adev->vcn.inst[i].ring_enc[0];  in vcn_v2_5_start()
1098 		ring = &adev->vcn.inst[i].ring_enc[1];  in vcn_v2_5_start()
1185 	for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {  in vcn_v2_5_sriov_start()
1196 		size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4);  in vcn_v2_5_sriov_start()
1214 				lower_32_bits(adev->vcn.inst[i].gpu_addr));  in vcn_v2_5_sriov_start()
1218 				upper_32_bits(adev->vcn.inst[i].gpu_addr));  in vcn_v2_5_sriov_start()
1231 			lower_32_bits(adev->vcn.inst[i].gpu_addr + offset));  in vcn_v2_5_sriov_start()
1235 			upper_32_bits(adev->vcn.inst[i].gpu_addr + offset));  in vcn_v2_5_sriov_start()
1245 			lower_32_bits(adev->vcn.inst[i].gpu_addr + offset +  in vcn_v2_5_sriov_start()
1250 			upper_32_bits(adev->vcn.inst[i].gpu_addr + offset +  in vcn_v2_5_sriov_start()
1259 		ring = &adev->vcn.inst[i].ring_enc[0];  in vcn_v2_5_sriov_start()
1272 		ring = &adev->vcn.inst[i].ring_dec;  in vcn_v2_5_sriov_start()
1339 	for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {  in vcn_v2_5_stop()
1340 		if (adev->vcn.harvest_config & (1 << i))  in vcn_v2_5_stop()
1410 	if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) {  in vcn_v2_5_pause_dpg_mode()
1412 			adev->vcn.inst[inst_idx].pause_state.fw_based,	new_state->fw_based);  in vcn_v2_5_pause_dpg_mode()
1421 				volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr;  in vcn_v2_5_pause_dpg_mode()
1439 				ring = &adev->vcn.inst[inst_idx].ring_enc[0];  in vcn_v2_5_pause_dpg_mode()
1449 				ring = &adev->vcn.inst[inst_idx].ring_enc[1];  in vcn_v2_5_pause_dpg_mode()
1471 		adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based;  in vcn_v2_5_pause_dpg_mode()
1600 	if (ring == &adev->vcn.inst[ring->me].ring_enc[0])  in vcn_v2_5_enc_ring_get_rptr()
1617 	if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) {  in vcn_v2_5_enc_ring_get_wptr()
1641 	if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) {  in vcn_v2_5_enc_ring_set_wptr()
1722 	for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {  in vcn_v2_5_set_dec_ring_funcs()
1723 		if (adev->vcn.harvest_config & (1 << i))  in vcn_v2_5_set_dec_ring_funcs()
1726 			adev->vcn.inst[i].ring_dec.funcs = &vcn_v2_5_dec_ring_vm_funcs;  in vcn_v2_5_set_dec_ring_funcs()
1728 			adev->vcn.inst[i].ring_dec.funcs = &vcn_v2_6_dec_ring_vm_funcs;  in vcn_v2_5_set_dec_ring_funcs()
1729 		adev->vcn.inst[i].ring_dec.me = i;  in vcn_v2_5_set_dec_ring_funcs()
1738 	for (j = 0; j < adev->vcn.num_vcn_inst; ++j) {  in vcn_v2_5_set_enc_ring_funcs()
1739 		if (adev->vcn.harvest_config & (1 << j))  in vcn_v2_5_set_enc_ring_funcs()
1741 		for (i = 0; i < adev->vcn.num_enc_rings; ++i) {  in vcn_v2_5_set_enc_ring_funcs()
1743 				adev->vcn.inst[j].ring_enc[i].funcs = &vcn_v2_5_enc_ring_vm_funcs;  in vcn_v2_5_set_enc_ring_funcs()
1745 				adev->vcn.inst[j].ring_enc[i].funcs = &vcn_v2_6_enc_ring_vm_funcs;  in vcn_v2_5_set_enc_ring_funcs()
1746 			adev->vcn.inst[j].ring_enc[i].me = j;  in vcn_v2_5_set_enc_ring_funcs()
1757 	for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {  in vcn_v2_5_is_idle()
1758 		if (adev->vcn.harvest_config & (1 << i))  in vcn_v2_5_is_idle()
1771 	for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {  in vcn_v2_5_wait_for_idle()
1772 		if (adev->vcn.harvest_config & (1 << i))  in vcn_v2_5_wait_for_idle()
1812 	if(state == adev->vcn.cur_state)  in vcn_v2_5_set_powergating_state()
1821 		adev->vcn.cur_state = state;  in vcn_v2_5_set_powergating_state()
1856 		amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_dec);  in vcn_v2_5_process_interrupt()
1859 		amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[0]);  in vcn_v2_5_process_interrupt()
1862 		amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[1]);  in vcn_v2_5_process_interrupt()
1885 	for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {  in vcn_v2_5_set_irq_funcs()
1886 		if (adev->vcn.harvest_config & (1 << i))  in vcn_v2_5_set_irq_funcs()
1888 		adev->vcn.inst[i].irq.num_types = adev->vcn.num_enc_rings + 1;  in vcn_v2_5_set_irq_funcs()
1889 		adev->vcn.inst[i].irq.funcs = &vcn_v2_5_irq_funcs;  in vcn_v2_5_set_irq_funcs()
1977 	for (inst = 0; inst < adev->vcn.num_vcn_inst; inst++)  in vcn_v2_6_query_poison_status()
1999 		adev->vcn.ras = &vcn_v2_6_ras;  in vcn_v2_5_set_ras_funcs()
2005 	if (adev->vcn.ras) {  in vcn_v2_5_set_ras_funcs()
2006 		amdgpu_ras_register_ras_block(adev, &adev->vcn.ras->ras_block);  in vcn_v2_5_set_ras_funcs()
2008 		strcpy(adev->vcn.ras->ras_block.ras_comm.name, "vcn");  in vcn_v2_5_set_ras_funcs()
2009 		adev->vcn.ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__VCN;  in vcn_v2_5_set_ras_funcs()
2010 		adev->vcn.ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__POISON;  in vcn_v2_5_set_ras_funcs()
2011 		adev->vcn.ras_if = &adev->vcn.ras->ras_block.ras_comm;  in vcn_v2_5_set_ras_funcs()
2014 		if (!adev->vcn.ras->ras_block.ras_late_init)  in vcn_v2_5_set_ras_funcs()
2015 			adev->vcn.ras->ras_block.ras_late_init = amdgpu_ras_block_late_init;  in vcn_v2_5_set_ras_funcs()