93 			harvest = RREG32_SOC15(VCN, i, mmCC_UVD_HARVESTING);  in vcn_v2_5_early_init()
173 		adev->vcn.inst[j].external.scratch9 = SOC15_REG_OFFSET(VCN, j, mmUVD_SCRATCH9);  in vcn_v2_5_sw_init()
175 		adev->vcn.inst[j].external.data0 = SOC15_REG_OFFSET(VCN, j, mmUVD_GPCOM_VCPU_DATA0);  in vcn_v2_5_sw_init()
177 		adev->vcn.inst[j].external.data1 = SOC15_REG_OFFSET(VCN, j, mmUVD_GPCOM_VCPU_DATA1);  in vcn_v2_5_sw_init()
179 		adev->vcn.inst[j].external.cmd = SOC15_REG_OFFSET(VCN, j, mmUVD_GPCOM_VCPU_CMD);  in vcn_v2_5_sw_init()
181 		adev->vcn.inst[j].external.nop = SOC15_REG_OFFSET(VCN, j, mmUVD_NO_OP);  in vcn_v2_5_sw_init()
339 		     RREG32_SOC15(VCN, i, mmUVD_STATUS)))  in vcn_v2_5_hw_fini()
406 			WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,  in vcn_v2_5_mc_resume()
408 			WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,  in vcn_v2_5_mc_resume()
410 			WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_OFFSET0, 0);  in vcn_v2_5_mc_resume()
413 			WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,  in vcn_v2_5_mc_resume()
415 			WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,  in vcn_v2_5_mc_resume()
418 			WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_OFFSET0,  in vcn_v2_5_mc_resume()
421 		WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_SIZE0, size);  in vcn_v2_5_mc_resume()
424 		WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,  in vcn_v2_5_mc_resume()
426 		WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,  in vcn_v2_5_mc_resume()
428 		WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_OFFSET1, 0);  in vcn_v2_5_mc_resume()
429 		WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE);  in vcn_v2_5_mc_resume()
432 		WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,  in vcn_v2_5_mc_resume()
434 		WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,  in vcn_v2_5_mc_resume()
436 		WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_OFFSET2, 0);  in vcn_v2_5_mc_resume()
437 		WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE);  in vcn_v2_5_mc_resume()
440 		WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW,  in vcn_v2_5_mc_resume()
442 		WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH,  in vcn_v2_5_mc_resume()
444 		WREG32_SOC15(VCN, i, mmUVD_VCPU_NONCACHE_OFFSET0, 0);  in vcn_v2_5_mc_resume()
445 		WREG32_SOC15(VCN, i, mmUVD_VCPU_NONCACHE_SIZE0,  in vcn_v2_5_mc_resume()
459 				VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),  in vcn_v2_5_mc_resume_dpg_mode()
462 				VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),  in vcn_v2_5_mc_resume_dpg_mode()
465 				VCN, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);  in vcn_v2_5_mc_resume_dpg_mode()
468 				VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect);  in vcn_v2_5_mc_resume_dpg_mode()
470 				VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect);  in vcn_v2_5_mc_resume_dpg_mode()
472 				VCN, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);  in vcn_v2_5_mc_resume_dpg_mode()
477 			VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),  in vcn_v2_5_mc_resume_dpg_mode()
480 			VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),  in vcn_v2_5_mc_resume_dpg_mode()
484 			VCN, 0, mmUVD_VCPU_CACHE_OFFSET0),  in vcn_v2_5_mc_resume_dpg_mode()
490 			VCN, 0, mmUVD_VCPU_CACHE_SIZE0), size, 0, indirect);  in vcn_v2_5_mc_resume_dpg_mode()
493 			VCN, 0, mmUVD_VCPU_CACHE_SIZE0), 0, 0, indirect);  in vcn_v2_5_mc_resume_dpg_mode()
498 			VCN, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),  in vcn_v2_5_mc_resume_dpg_mode()
501 			VCN, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),  in vcn_v2_5_mc_resume_dpg_mode()
504 			VCN, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);  in vcn_v2_5_mc_resume_dpg_mode()
507 			VCN, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect);  in vcn_v2_5_mc_resume_dpg_mode()
509 			VCN, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect);  in vcn_v2_5_mc_resume_dpg_mode()
511 			VCN, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);  in vcn_v2_5_mc_resume_dpg_mode()
514 		VCN, 0, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect);  in vcn_v2_5_mc_resume_dpg_mode()
518 		VCN, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),  in vcn_v2_5_mc_resume_dpg_mode()
521 		VCN, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),  in vcn_v2_5_mc_resume_dpg_mode()
524 		VCN, 0, mmUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect);  in vcn_v2_5_mc_resume_dpg_mode()
526 		VCN, 0, mmUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect);  in vcn_v2_5_mc_resume_dpg_mode()
530 		VCN, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW),  in vcn_v2_5_mc_resume_dpg_mode()
533 		VCN, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH),  in vcn_v2_5_mc_resume_dpg_mode()
536 		VCN, 0, mmUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect);  in vcn_v2_5_mc_resume_dpg_mode()
538 		VCN, 0, mmUVD_VCPU_NONCACHE_SIZE0),  in vcn_v2_5_mc_resume_dpg_mode()
543 		VCN, 0, mmUVD_GFX8_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect);  in vcn_v2_5_mc_resume_dpg_mode()
562 		data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL);  in vcn_v2_5_disable_clock_gating()
569 		WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data);  in vcn_v2_5_disable_clock_gating()
571 		data = RREG32_SOC15(VCN, i, mmUVD_CGC_GATE);  in vcn_v2_5_disable_clock_gating()
593 		WREG32_SOC15(VCN, i, mmUVD_CGC_GATE, data);  in vcn_v2_5_disable_clock_gating()
595 		SOC15_WAIT_ON_RREG(VCN, i, mmUVD_CGC_GATE, 0,  0xFFFFFFFF);  in vcn_v2_5_disable_clock_gating()
597 		data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL);  in vcn_v2_5_disable_clock_gating()
618 		WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data);  in vcn_v2_5_disable_clock_gating()
621 		data = RREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_GATE);  in vcn_v2_5_disable_clock_gating()
646 		WREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_GATE, data);  in vcn_v2_5_disable_clock_gating()
648 		data = RREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_CTRL);  in vcn_v2_5_disable_clock_gating()
659 		WREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_CTRL, data);  in vcn_v2_5_disable_clock_gating()
696 		VCN, 0, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect);  in vcn_v2_5_clock_gating_dpg_mode()
700 		VCN, 0, mmUVD_CGC_GATE), 0, sram_sel, indirect);  in vcn_v2_5_clock_gating_dpg_mode()
704 		VCN, 0, mmUVD_SUVD_CGC_GATE), 1, sram_sel, indirect);  in vcn_v2_5_clock_gating_dpg_mode()
708 		VCN, 0, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect);  in vcn_v2_5_clock_gating_dpg_mode()
727 		data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL);  in vcn_v2_5_enable_clock_gating()
734 		WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data);  in vcn_v2_5_enable_clock_gating()
736 		data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL);  in vcn_v2_5_enable_clock_gating()
756 		WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data);  in vcn_v2_5_enable_clock_gating()
758 		data = RREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_CTRL);  in vcn_v2_5_enable_clock_gating()
769 		WREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_CTRL, data);  in vcn_v2_5_enable_clock_gating()
780 	WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1,  in vcn_v2_5_start_dpg_mode()
783 	tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_POWER_STATUS);  in vcn_v2_5_start_dpg_mode()
786 	WREG32_SOC15(VCN, inst_idx, mmUVD_POWER_STATUS, tmp);  in vcn_v2_5_start_dpg_mode()
799 		VCN, 0, mmUVD_VCPU_CNTL), tmp, 0, indirect);  in vcn_v2_5_start_dpg_mode()
803 		VCN, 0, mmUVD_MASTINT_EN), 0, 0, indirect);  in vcn_v2_5_start_dpg_mode()
815 		VCN, 0, mmUVD_LMI_CTRL), tmp, 0, indirect);  in vcn_v2_5_start_dpg_mode()
818 		VCN, 0, mmUVD_MPC_CNTL),  in vcn_v2_5_start_dpg_mode()
822 		VCN, 0, mmUVD_MPC_SET_MUXA0),  in vcn_v2_5_start_dpg_mode()
829 		VCN, 0, mmUVD_MPC_SET_MUXB0),  in vcn_v2_5_start_dpg_mode()
836 		VCN, 0, mmUVD_MPC_SET_MUX),  in vcn_v2_5_start_dpg_mode()
844 		VCN, 0, mmUVD_REG_XX_MASK), 0x10, 0, indirect);  in vcn_v2_5_start_dpg_mode()
846 		VCN, 0, mmUVD_RBC_XX_IB_REG_CHECK), 0x3, 0, indirect);  in vcn_v2_5_start_dpg_mode()
850 		VCN, 0, mmUVD_LMI_CTRL2), 0, 0, indirect);  in vcn_v2_5_start_dpg_mode()
854 		VCN, 0, mmUVD_RB_ARB_CTRL), 0, 0, indirect);  in vcn_v2_5_start_dpg_mode()
859 		VCN, 0, mmUVD_VCPU_CNTL), tmp, 0, indirect);  in vcn_v2_5_start_dpg_mode()
863 		VCN, 0, mmUVD_MASTINT_EN),  in vcn_v2_5_start_dpg_mode()
879 	WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_CNTL, tmp);  in vcn_v2_5_start_dpg_mode()
882 	WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS),  in vcn_v2_5_start_dpg_mode()
888 	WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR_CNTL, 0);  in vcn_v2_5_start_dpg_mode()
891 	WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR_ADDR,  in vcn_v2_5_start_dpg_mode()
895 	WREG32_SOC15(VCN, inst_idx, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,  in vcn_v2_5_start_dpg_mode()
897 	WREG32_SOC15(VCN, inst_idx, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,  in vcn_v2_5_start_dpg_mode()
901 	WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR, 0);  in vcn_v2_5_start_dpg_mode()
903 	WREG32_SOC15(VCN, inst_idx, mmUVD_SCRATCH2, 0);  in vcn_v2_5_start_dpg_mode()
905 	ring->wptr = RREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR);  in vcn_v2_5_start_dpg_mode()
906 	WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR,  in vcn_v2_5_start_dpg_mode()
911 	WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS),  in vcn_v2_5_start_dpg_mode()
935 		WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_POWER_STATUS), 0,  in vcn_v2_5_start()
939 		tmp = RREG32_SOC15(VCN, i, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY;  in vcn_v2_5_start()
940 		WREG32_SOC15(VCN, i, mmUVD_STATUS, tmp);  in vcn_v2_5_start()
953 		WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL),  in vcn_v2_5_start()
957 		WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN), 0,  in vcn_v2_5_start()
961 		tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL);  in vcn_v2_5_start()
963 		WREG32_SOC15(VCN, i, mmUVD_LMI_CTRL, tmp | 0x8|  in vcn_v2_5_start()
970 		tmp = RREG32_SOC15(VCN, i, mmUVD_MPC_CNTL);  in vcn_v2_5_start()
973 		WREG32_SOC15(VCN, i, mmUVD_MPC_CNTL, tmp);  in vcn_v2_5_start()
976 		WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUXA0,  in vcn_v2_5_start()
983 		WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUXB0,  in vcn_v2_5_start()
990 		WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUX,  in vcn_v2_5_start()
1003 		WREG32_SOC15(VCN, i, mmUVD_GFX8_ADDR_CONFIG,  in vcn_v2_5_start()
1005 		WREG32_SOC15(VCN, i, mmUVD_GFX8_ADDR_CONFIG,  in vcn_v2_5_start()
1009 		WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_LMI_CTRL2), 0,  in vcn_v2_5_start()
1013 		WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_RB_ARB_CTRL), 0,  in vcn_v2_5_start()
1016 		WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0,  in vcn_v2_5_start()
1023 				status = RREG32_SOC15(VCN, i, mmUVD_STATUS);  in vcn_v2_5_start()
1036 			WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL),  in vcn_v2_5_start()
1040 			WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0,  in vcn_v2_5_start()
1053 		WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN),  in vcn_v2_5_start()
1058 		WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_STATUS), 0,  in vcn_v2_5_start()
1061 		WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_VMID, 0);  in vcn_v2_5_start()
1071 		WREG32_SOC15(VCN, i, mmUVD_RBC_RB_CNTL, tmp);  in vcn_v2_5_start()
1075 		WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,  in vcn_v2_5_start()
1077 		WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,  in vcn_v2_5_start()
1081 		WREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR, 0);  in vcn_v2_5_start()
1083 		ring->wptr = RREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR);  in vcn_v2_5_start()
1084 		WREG32_SOC15(VCN, i, mmUVD_RBC_RB_WPTR,  in vcn_v2_5_start()
1090 		WREG32_SOC15(VCN, i, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));  in vcn_v2_5_start()
1091 		WREG32_SOC15(VCN, i, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));  in vcn_v2_5_start()
1092 		WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO, ring->gpu_addr);  in vcn_v2_5_start()
1093 		WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));  in vcn_v2_5_start()
1094 		WREG32_SOC15(VCN, i, mmUVD_RB_SIZE, ring->ring_size / 4);  in vcn_v2_5_start()
1099 		WREG32_SOC15(VCN, i, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));  in vcn_v2_5_start()
1100 		WREG32_SOC15(VCN, i, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));  in vcn_v2_5_start()
1101 		WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO2, ring->gpu_addr);  in vcn_v2_5_start()
1102 		WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));  in vcn_v2_5_start()
1103 		WREG32_SOC15(VCN, i, mmUVD_RB_SIZE2, ring->ring_size / 4);  in vcn_v2_5_start()
1124 	WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_ADDR_LO, lower_32_bits(addr));  in vcn_v2_5_mmsch_start()
1125 	WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_ADDR_HI, upper_32_bits(addr));  in vcn_v2_5_mmsch_start()
1128 	data = RREG32_SOC15(VCN, 0, mmMMSCH_VF_VMID);  in vcn_v2_5_mmsch_start()
1132 	WREG32_SOC15(VCN, 0, mmMMSCH_VF_VMID, data);  in vcn_v2_5_mmsch_start()
1135 	WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_SIZE, size);  in vcn_v2_5_mmsch_start()
1138 	WREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_RESP, 0);  in vcn_v2_5_mmsch_start()
1144 	WREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_HOST, 0x10000001);  in vcn_v2_5_mmsch_start()
1146 	data = RREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_RESP);  in vcn_v2_5_mmsch_start()
1150 		data = RREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_RESP);  in vcn_v2_5_mmsch_start()
1193 			SOC15_REG_OFFSET(VCN, i, mmUVD_STATUS),  in vcn_v2_5_sriov_start()
1200 				SOC15_REG_OFFSET(VCN, i,  in vcn_v2_5_sriov_start()
1204 				SOC15_REG_OFFSET(VCN, i,  in vcn_v2_5_sriov_start()
1209 				SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_OFFSET0), 0);  in vcn_v2_5_sriov_start()
1212 				SOC15_REG_OFFSET(VCN, i,  in vcn_v2_5_sriov_start()
1216 				SOC15_REG_OFFSET(VCN, i,  in vcn_v2_5_sriov_start()
1221 				SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_OFFSET0),  in vcn_v2_5_sriov_start()
1226 			SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_SIZE0),  in vcn_v2_5_sriov_start()
1229 			SOC15_REG_OFFSET(VCN, i,  in vcn_v2_5_sriov_start()
1233 			SOC15_REG_OFFSET(VCN, i,  in vcn_v2_5_sriov_start()
1237 			SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_OFFSET1),  in vcn_v2_5_sriov_start()
1240 			SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_SIZE1),  in vcn_v2_5_sriov_start()
1243 			SOC15_REG_OFFSET(VCN, i,  in vcn_v2_5_sriov_start()
1248 			SOC15_REG_OFFSET(VCN, i,  in vcn_v2_5_sriov_start()
1253 			SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_OFFSET2),  in vcn_v2_5_sriov_start()
1256 			SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_SIZE2),  in vcn_v2_5_sriov_start()
1263 			SOC15_REG_OFFSET(VCN, i, mmUVD_RB_BASE_LO),  in vcn_v2_5_sriov_start()
1266 			SOC15_REG_OFFSET(VCN, i, mmUVD_RB_BASE_HI),  in vcn_v2_5_sriov_start()
1269 			SOC15_REG_OFFSET(VCN, i, mmUVD_RB_SIZE),  in vcn_v2_5_sriov_start()
1275 			SOC15_REG_OFFSET(VCN, i,  in vcn_v2_5_sriov_start()
1279 			SOC15_REG_OFFSET(VCN, i,  in vcn_v2_5_sriov_start()
1291 			SOC15_REG_OFFSET(VCN, i, mmUVD_RBC_RB_CNTL), tmp);  in vcn_v2_5_sriov_start()
1311 	SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1,  in vcn_v2_5_stop_dpg_mode()
1315 	tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR);  in vcn_v2_5_stop_dpg_mode()
1316 	SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF);  in vcn_v2_5_stop_dpg_mode()
1318 	tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR2);  in vcn_v2_5_stop_dpg_mode()
1319 	SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF);  in vcn_v2_5_stop_dpg_mode()
1321 	tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF;  in vcn_v2_5_stop_dpg_mode()
1322 	SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF);  in vcn_v2_5_stop_dpg_mode()
1324 	SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1,  in vcn_v2_5_stop_dpg_mode()
1328 	WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 0,  in vcn_v2_5_stop_dpg_mode()
1348 		r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7);  in vcn_v2_5_stop()
1356 		r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp);  in vcn_v2_5_stop()
1361 		tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2);  in vcn_v2_5_stop()
1363 		WREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2, tmp);  in vcn_v2_5_stop()
1367 		r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp);  in vcn_v2_5_stop()
1372 		WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_RB_ARB_CTRL),  in vcn_v2_5_stop()
1377 		WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL),  in vcn_v2_5_stop()
1382 		WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0,  in vcn_v2_5_stop()
1386 		WREG32_SOC15(VCN, i, mmUVD_STATUS, 0);  in vcn_v2_5_stop()
1391 		WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_POWER_STATUS),  in vcn_v2_5_stop()
1413 		reg_data = RREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE) &  in vcn_v2_5_pause_dpg_mode()
1417 			ret_code = SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 0x1,  in vcn_v2_5_pause_dpg_mode()
1425 				WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE, reg_data);  in vcn_v2_5_pause_dpg_mode()
1428 				SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_DPG_PAUSE,  in vcn_v2_5_pause_dpg_mode()
1433 				WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS),  in vcn_v2_5_pause_dpg_mode()
1441 				WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_LO, ring->gpu_addr);  in vcn_v2_5_pause_dpg_mode()
1442 				WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));  in vcn_v2_5_pause_dpg_mode()
1443 				WREG32_SOC15(VCN, inst_idx, mmUVD_RB_SIZE, ring->ring_size / 4);  in vcn_v2_5_pause_dpg_mode()
1444 				WREG32_SOC15(VCN, inst_idx, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));  in vcn_v2_5_pause_dpg_mode()
1445 				WREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));  in vcn_v2_5_pause_dpg_mode()
1451 				WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_LO2, ring->gpu_addr);  in vcn_v2_5_pause_dpg_mode()
1452 				WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));  in vcn_v2_5_pause_dpg_mode()
1453 				WREG32_SOC15(VCN, inst_idx, mmUVD_RB_SIZE2, ring->ring_size / 4);  in vcn_v2_5_pause_dpg_mode()
1454 				WREG32_SOC15(VCN, inst_idx, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));  in vcn_v2_5_pause_dpg_mode()
1455 				WREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));  in vcn_v2_5_pause_dpg_mode()
1459 				WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS),  in vcn_v2_5_pause_dpg_mode()
1462 				SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS,  in vcn_v2_5_pause_dpg_mode()
1467 			WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE, reg_data);  in vcn_v2_5_pause_dpg_mode()
1468 			SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 0x1,  in vcn_v2_5_pause_dpg_mode()
1488 	return RREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_RPTR);  in vcn_v2_5_dec_ring_get_rptr()
1505 		return RREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_WPTR);  in vcn_v2_5_dec_ring_get_wptr()
1523 		WREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));  in vcn_v2_5_dec_ring_set_wptr()
1601 		return RREG32_SOC15(VCN, ring->me, mmUVD_RB_RPTR);  in vcn_v2_5_enc_ring_get_rptr()
1603 		return RREG32_SOC15(VCN, ring->me, mmUVD_RB_RPTR2);  in vcn_v2_5_enc_ring_get_rptr()
1621 			return RREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR);  in vcn_v2_5_enc_ring_get_wptr()
1626 			return RREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR2);  in vcn_v2_5_enc_ring_get_wptr()
1646 			WREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));  in vcn_v2_5_enc_ring_set_wptr()
1653 			WREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));  in vcn_v2_5_enc_ring_set_wptr()
1760 		ret &= (RREG32_SOC15(VCN, i, mmUVD_STATUS) == UVD_STATUS__IDLE);  in vcn_v2_5_is_idle()
1774 		ret = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE,  in vcn_v2_5_wait_for_idle()
1958 		reg_value = RREG32_SOC15(VCN, instance, mmUVD_RAS_VCPU_VCODEC_STATUS);  in vcn_v2_6_query_poison_by_instance()