76 		adev->vcn.num_enc_rings = 1;  in vcn_v2_0_early_init()
78 		adev->vcn.num_enc_rings = 2;  in vcn_v2_0_early_init()
104 			      &adev->vcn.inst->irq);  in vcn_v2_0_sw_init()
109 	for (i = 0; i < adev->vcn.num_enc_rings; ++i) {  in vcn_v2_0_sw_init()
112 				      &adev->vcn.inst->irq);  in vcn_v2_0_sw_init()
127 	ring = &adev->vcn.inst->ring_dec;  in vcn_v2_0_sw_init()
130 	ring->doorbell_index = adev->doorbell_index.vcn.vcn_ring0_1 << 1;  in vcn_v2_0_sw_init()
133 	r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0,  in vcn_v2_0_sw_init()
138 	adev->vcn.internal.context_id = mmUVD_CONTEXT_ID_INTERNAL_OFFSET;  in vcn_v2_0_sw_init()
139 	adev->vcn.internal.ib_vmid = mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET;  in vcn_v2_0_sw_init()
140 	adev->vcn.internal.ib_bar_low = mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET;  in vcn_v2_0_sw_init()
141 	adev->vcn.internal.ib_bar_high = mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET;  in vcn_v2_0_sw_init()
142 	adev->vcn.internal.ib_size = mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET;  in vcn_v2_0_sw_init()
143 	adev->vcn.internal.gp_scratch8 = mmUVD_GP_SCRATCH8_INTERNAL_OFFSET;  in vcn_v2_0_sw_init()
145 	adev->vcn.internal.scratch9 = mmUVD_SCRATCH9_INTERNAL_OFFSET;  in vcn_v2_0_sw_init()
146 	adev->vcn.inst->external.scratch9 = SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9);  in vcn_v2_0_sw_init()
147 	adev->vcn.internal.data0 = mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET;  in vcn_v2_0_sw_init()
148 	adev->vcn.inst->external.data0 = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0);  in vcn_v2_0_sw_init()
149 	adev->vcn.internal.data1 = mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET;  in vcn_v2_0_sw_init()
150 	adev->vcn.inst->external.data1 = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1);  in vcn_v2_0_sw_init()
151 	adev->vcn.internal.cmd = mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET;  in vcn_v2_0_sw_init()
152 	adev->vcn.inst->external.cmd = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD);  in vcn_v2_0_sw_init()
153 	adev->vcn.internal.nop = mmUVD_NO_OP_INTERNAL_OFFSET;  in vcn_v2_0_sw_init()
154 	adev->vcn.inst->external.nop = SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP);  in vcn_v2_0_sw_init()
156 	for (i = 0; i < adev->vcn.num_enc_rings; ++i) {  in vcn_v2_0_sw_init()
159 		ring = &adev->vcn.inst->ring_enc[i];  in vcn_v2_0_sw_init()
162 			ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 2 + i;  in vcn_v2_0_sw_init()
164 			ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 1 + i;  in vcn_v2_0_sw_init()
166 		r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0,  in vcn_v2_0_sw_init()
172 	adev->vcn.pause_dpg_mode = vcn_v2_0_pause_dpg_mode;  in vcn_v2_0_sw_init()
178 	fw_shared = adev->vcn.inst->fw_shared.cpu_addr;  in vcn_v2_0_sw_init()
182 		amdgpu_vcn_fwlog_init(adev->vcn.inst);  in vcn_v2_0_sw_init()
198 	volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst->fw_shared.cpu_addr;  in vcn_v2_0_sw_fini()
226 	struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec;  in vcn_v2_0_hw_init()
243 	for (i = 0; i < adev->vcn.num_enc_rings; ++i) {  in vcn_v2_0_hw_init()
244 		ring = &adev->vcn.inst->ring_enc[i];  in vcn_v2_0_hw_init()
269 	cancel_delayed_work_sync(&adev->vcn.idle_work);  in vcn_v2_0_hw_fini()
272 	    (adev->vcn.cur_state != AMD_PG_STATE_GATE &&  in vcn_v2_0_hw_fini()
330 	uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4);  in vcn_v2_0_mc_resume()
346 			lower_32_bits(adev->vcn.inst->gpu_addr));  in vcn_v2_0_mc_resume()
348 			upper_32_bits(adev->vcn.inst->gpu_addr));  in vcn_v2_0_mc_resume()
358 		lower_32_bits(adev->vcn.inst->gpu_addr + offset));  in vcn_v2_0_mc_resume()
360 		upper_32_bits(adev->vcn.inst->gpu_addr + offset));  in vcn_v2_0_mc_resume()
366 		lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));  in vcn_v2_0_mc_resume()
368 		upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));  in vcn_v2_0_mc_resume()
374 		lower_32_bits(adev->vcn.inst->fw_shared.gpu_addr));  in vcn_v2_0_mc_resume()
376 		upper_32_bits(adev->vcn.inst->fw_shared.gpu_addr));  in vcn_v2_0_mc_resume()
386 	uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4);  in vcn_v2_0_mc_resume_dpg_mode()
412 			lower_32_bits(adev->vcn.inst->gpu_addr), 0, indirect);  in vcn_v2_0_mc_resume_dpg_mode()
415 			upper_32_bits(adev->vcn.inst->gpu_addr), 0, indirect);  in vcn_v2_0_mc_resume_dpg_mode()
433 			lower_32_bits(adev->vcn.inst->gpu_addr + offset), 0, indirect);  in vcn_v2_0_mc_resume_dpg_mode()
436 			upper_32_bits(adev->vcn.inst->gpu_addr + offset), 0, indirect);  in vcn_v2_0_mc_resume_dpg_mode()
453 		lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);  in vcn_v2_0_mc_resume_dpg_mode()
456 		upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);  in vcn_v2_0_mc_resume_dpg_mode()
465 		lower_32_bits(adev->vcn.inst->fw_shared.gpu_addr), 0, indirect);  in vcn_v2_0_mc_resume_dpg_mode()
468 		upper_32_bits(adev->vcn.inst->fw_shared.gpu_addr), 0, indirect);  in vcn_v2_0_mc_resume_dpg_mode()
794 	volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst->fw_shared.cpu_addr;  in vcn_v2_0_start_dpg_mode()
795 	struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec;  in vcn_v2_0_start_dpg_mode()
807 		adev->vcn.inst->dpg_sram_curr_addr = (uint32_t *)adev->vcn.inst->dpg_sram_cpu_addr;  in vcn_v2_0_start_dpg_mode()
881 		psp_update_vcn_sram(adev, 0, adev->vcn.inst->dpg_sram_gpu_addr,  in vcn_v2_0_start_dpg_mode()
882 				    (uint32_t)((uintptr_t)adev->vcn.inst->dpg_sram_curr_addr -  in vcn_v2_0_start_dpg_mode()
883 					       (uintptr_t)adev->vcn.inst->dpg_sram_cpu_addr));  in vcn_v2_0_start_dpg_mode()
931 	volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst->fw_shared.cpu_addr;  in vcn_v2_0_start()
932 	struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec;  in vcn_v2_0_start()
941 		return vcn_v2_0_start_dpg_mode(adev, adev->vcn.indirect_sram);  in vcn_v2_0_start()
1082 	ring = &adev->vcn.inst->ring_enc[0];  in vcn_v2_0_start()
1091 	ring = &adev->vcn.inst->ring_enc[1];  in vcn_v2_0_start()
1208 	if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) {  in vcn_v2_0_pause_dpg_mode()
1210 			adev->vcn.inst[inst_idx].pause_state.fw_based,	new_state->fw_based);  in vcn_v2_0_pause_dpg_mode()
1219 				volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst->fw_shared.cpu_addr;  in vcn_v2_0_pause_dpg_mode()
1235 				ring = &adev->vcn.inst->ring_enc[0];  in vcn_v2_0_pause_dpg_mode()
1245 				ring = &adev->vcn.inst->ring_enc[1];  in vcn_v2_0_pause_dpg_mode()
1271 		adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based;  in vcn_v2_0_pause_dpg_mode()
1381 	amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0));  in vcn_v2_0_dec_ring_insert_start()
1383 	amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0));  in vcn_v2_0_dec_ring_insert_start()
1398 	amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0));  in vcn_v2_0_dec_ring_insert_end()
1418 		amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.nop, 0));  in vcn_v2_0_dec_ring_insert_nop()
1439 	amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.context_id, 0));  in vcn_v2_0_dec_ring_emit_fence()
1442 	amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0));  in vcn_v2_0_dec_ring_emit_fence()
1445 	amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data1, 0));  in vcn_v2_0_dec_ring_emit_fence()
1448 	amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0));  in vcn_v2_0_dec_ring_emit_fence()
1451 	amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0));  in vcn_v2_0_dec_ring_emit_fence()
1454 	amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data1, 0));  in vcn_v2_0_dec_ring_emit_fence()
1457 	amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0));  in vcn_v2_0_dec_ring_emit_fence()
1480 	amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.ib_vmid, 0));  in vcn_v2_0_dec_ring_emit_ib()
1483 	amdgpu_ring_write(ring,	PACKET0(adev->vcn.internal.ib_bar_low, 0));  in vcn_v2_0_dec_ring_emit_ib()
1485 	amdgpu_ring_write(ring,	PACKET0(adev->vcn.internal.ib_bar_high, 0));  in vcn_v2_0_dec_ring_emit_ib()
1487 	amdgpu_ring_write(ring,	PACKET0(adev->vcn.internal.ib_size, 0));  in vcn_v2_0_dec_ring_emit_ib()
1496 	amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0));  in vcn_v2_0_dec_ring_emit_reg_wait()
1499 	amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data1, 0));  in vcn_v2_0_dec_ring_emit_reg_wait()
1502 	amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.gp_scratch8, 0));  in vcn_v2_0_dec_ring_emit_reg_wait()
1505 	amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0));  in vcn_v2_0_dec_ring_emit_reg_wait()
1530 	amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0));  in vcn_v2_0_dec_ring_emit_wreg()
1533 	amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data1, 0));  in vcn_v2_0_dec_ring_emit_wreg()
1536 	amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0));  in vcn_v2_0_dec_ring_emit_wreg()
1552 	if (ring == &adev->vcn.inst->ring_enc[0])  in vcn_v2_0_enc_ring_get_rptr()
1569 	if (ring == &adev->vcn.inst->ring_enc[0]) {  in vcn_v2_0_enc_ring_get_wptr()
1593 	if (ring == &adev->vcn.inst->ring_enc[0]) {  in vcn_v2_0_enc_ring_set_wptr()
1706 		amdgpu_fence_process(&adev->vcn.inst->ring_dec);  in vcn_v2_0_process_interrupt()
1709 		amdgpu_fence_process(&adev->vcn.inst->ring_enc[0]);  in vcn_v2_0_process_interrupt()
1712 		amdgpu_fence_process(&adev->vcn.inst->ring_enc[1]);  in vcn_v2_0_process_interrupt()
1733 	WREG32(adev->vcn.inst[ring->me].external.scratch9, 0xCAFEDEAD);  in vcn_v2_0_dec_ring_test_ring()
1737 	amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0));  in vcn_v2_0_dec_ring_test_ring()
1739 	amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.scratch9, 0));  in vcn_v2_0_dec_ring_test_ring()
1743 		tmp = RREG32(adev->vcn.inst[ring->me].external.scratch9);  in vcn_v2_0_dec_ring_test_ring()
1770 		adev->vcn.cur_state = AMD_PG_STATE_UNGATE;  in vcn_v2_0_set_powergating_state()
1774 	if (state == adev->vcn.cur_state)  in vcn_v2_0_set_powergating_state()
1783 		adev->vcn.cur_state = state;  in vcn_v2_0_set_powergating_state()
1818 	adev->vcn.inst->ring_dec.wptr = 0;  in vcn_v2_0_start_mmsch()
1819 	adev->vcn.inst->ring_dec.wptr_old = 0;  in vcn_v2_0_start_mmsch()
1820 	vcn_v2_0_dec_ring_set_wptr(&adev->vcn.inst->ring_dec);  in vcn_v2_0_start_mmsch()
1822 	for (i = 0; i < adev->vcn.num_enc_rings; ++i) {  in vcn_v2_0_start_mmsch()
1823 		adev->vcn.inst->ring_enc[i].wptr = 0;  in vcn_v2_0_start_mmsch()
1824 		adev->vcn.inst->ring_enc[i].wptr_old = 0;  in vcn_v2_0_start_mmsch()
1825 		vcn_v2_0_enc_ring_set_wptr(&adev->vcn.inst->ring_enc[i]);  in vcn_v2_0_start_mmsch()
1880 		size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4);  in vcn_v2_0_start_sriov()
1901 				lower_32_bits(adev->vcn.inst->gpu_addr));  in vcn_v2_0_start_sriov()
1905 				upper_32_bits(adev->vcn.inst->gpu_addr));  in vcn_v2_0_start_sriov()
1919 			lower_32_bits(adev->vcn.inst->gpu_addr + offset));  in vcn_v2_0_start_sriov()
1923 			upper_32_bits(adev->vcn.inst->gpu_addr + offset));  in vcn_v2_0_start_sriov()
1934 			lower_32_bits(adev->vcn.inst->gpu_addr + offset +  in vcn_v2_0_start_sriov()
1939 			upper_32_bits(adev->vcn.inst->gpu_addr + offset +  in vcn_v2_0_start_sriov()
1948 		for (r = 0; r < adev->vcn.num_enc_rings; ++r) {  in vcn_v2_0_start_sriov()
1949 			ring = &adev->vcn.inst->ring_enc[r];  in vcn_v2_0_start_sriov()
1962 		ring = &adev->vcn.inst->ring_dec;  in vcn_v2_0_start_sriov()
2075 	adev->vcn.inst->ring_dec.funcs = &vcn_v2_0_dec_ring_vm_funcs;  in vcn_v2_0_set_dec_ring_funcs()
2083 	for (i = 0; i < adev->vcn.num_enc_rings; ++i)  in vcn_v2_0_set_enc_ring_funcs()
2084 		adev->vcn.inst->ring_enc[i].funcs = &vcn_v2_0_enc_ring_vm_funcs;  in vcn_v2_0_set_enc_ring_funcs()
2096 	adev->vcn.inst->irq.num_types = adev->vcn.num_enc_rings + 1;  in vcn_v2_0_set_irq_funcs()
2097 	adev->vcn.inst->irq.funcs = &vcn_v2_0_irq_funcs;  in vcn_v2_0_set_irq_funcs()