239 		 RREG32_SOC15(VCN, 0, mmUVD_STATUS))) {  in vcn_v1_0_hw_fini()
453 	data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL);  in vcn_v1_0_disable_clock_gating()
462 	WREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL, data);  in vcn_v1_0_disable_clock_gating()
464 	data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE);  in vcn_v1_0_disable_clock_gating()
466 	WREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE, data);  in vcn_v1_0_disable_clock_gating()
469 	data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);  in vcn_v1_0_disable_clock_gating()
477 	WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);  in vcn_v1_0_disable_clock_gating()
479 	data = RREG32_SOC15(VCN, 0, mmUVD_CGC_GATE);  in vcn_v1_0_disable_clock_gating()
500 	WREG32_SOC15(VCN, 0, mmUVD_CGC_GATE, data);  in vcn_v1_0_disable_clock_gating()
502 	data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);  in vcn_v1_0_disable_clock_gating()
523 	WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);  in vcn_v1_0_disable_clock_gating()
526 	data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE);  in vcn_v1_0_disable_clock_gating()
551 	WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE, data);  in vcn_v1_0_disable_clock_gating()
553 	data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL);  in vcn_v1_0_disable_clock_gating()
564 	WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data);  in vcn_v1_0_disable_clock_gating()
579 	data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL);  in vcn_v1_0_enable_clock_gating()
586 	WREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL, data);  in vcn_v1_0_enable_clock_gating()
588 	data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE);  in vcn_v1_0_enable_clock_gating()
590 	WREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE, data);  in vcn_v1_0_enable_clock_gating()
593 	data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);  in vcn_v1_0_enable_clock_gating()
600 	WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);  in vcn_v1_0_enable_clock_gating()
602 	data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);  in vcn_v1_0_enable_clock_gating()
623 	WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);  in vcn_v1_0_enable_clock_gating()
625 	data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL);  in vcn_v1_0_enable_clock_gating()
636 	WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data);  in vcn_v1_0_enable_clock_gating()
710 		WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data);  in vcn_1_0_disable_static_power_gating()
711 		SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON, 0xFFFFFF);  in vcn_1_0_disable_static_power_gating()
724 		WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data);  in vcn_1_0_disable_static_power_gating()
725 		SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, 0,  0xFFFFFFFF);  in vcn_1_0_disable_static_power_gating()
730 	data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS);  in vcn_1_0_disable_static_power_gating()
735 	WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data);  in vcn_1_0_disable_static_power_gating()
744 		data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS);  in vcn_1_0_enable_static_power_gating()
747 		WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data);  in vcn_1_0_enable_static_power_gating()
762 		WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data);  in vcn_1_0_enable_static_power_gating()
775 		SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, data, 0xFFFFFFFF);  in vcn_1_0_enable_static_power_gating()
1340 	return (RREG32_SOC15(VCN, 0, mmUVD_STATUS) == UVD_STATUS__IDLE);  in vcn_v1_0_is_idle()
1348 	ret = SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE,  in vcn_v1_0_wait_for_idle()