Lines Matching refs:adev
77 static int soc21_query_video_codecs(struct amdgpu_device *adev, bool encode, in soc21_query_video_codecs() argument
80 switch (adev->ip_versions[UVD_HWIP][0]) { in soc21_query_video_codecs()
96 static u32 soc21_pcie_rreg(struct amdgpu_device *adev, u32 reg) in soc21_pcie_rreg() argument
99 address = adev->nbio.funcs->get_pcie_index_offset(adev); in soc21_pcie_rreg()
100 data = adev->nbio.funcs->get_pcie_data_offset(adev); in soc21_pcie_rreg()
102 return amdgpu_device_indirect_rreg(adev, address, data, reg); in soc21_pcie_rreg()
105 static void soc21_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v) in soc21_pcie_wreg() argument
109 address = adev->nbio.funcs->get_pcie_index_offset(adev); in soc21_pcie_wreg()
110 data = adev->nbio.funcs->get_pcie_data_offset(adev); in soc21_pcie_wreg()
112 amdgpu_device_indirect_wreg(adev, address, data, reg, v); in soc21_pcie_wreg()
115 static u64 soc21_pcie_rreg64(struct amdgpu_device *adev, u32 reg) in soc21_pcie_rreg64() argument
118 address = adev->nbio.funcs->get_pcie_index_offset(adev); in soc21_pcie_rreg64()
119 data = adev->nbio.funcs->get_pcie_data_offset(adev); in soc21_pcie_rreg64()
121 return amdgpu_device_indirect_rreg64(adev, address, data, reg); in soc21_pcie_rreg64()
124 static void soc21_pcie_wreg64(struct amdgpu_device *adev, u32 reg, u64 v) in soc21_pcie_wreg64() argument
128 address = adev->nbio.funcs->get_pcie_index_offset(adev); in soc21_pcie_wreg64()
129 data = adev->nbio.funcs->get_pcie_data_offset(adev); in soc21_pcie_wreg64()
131 amdgpu_device_indirect_wreg64(adev, address, data, reg, v); in soc21_pcie_wreg64()
134 static u32 soc21_didt_rreg(struct amdgpu_device *adev, u32 reg) in soc21_didt_rreg() argument
142 spin_lock_irqsave(&adev->didt_idx_lock, flags); in soc21_didt_rreg()
145 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); in soc21_didt_rreg()
149 static void soc21_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) in soc21_didt_wreg() argument
156 spin_lock_irqsave(&adev->didt_idx_lock, flags); in soc21_didt_wreg()
159 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); in soc21_didt_wreg()
162 static u32 soc21_get_config_memsize(struct amdgpu_device *adev) in soc21_get_config_memsize() argument
164 return adev->nbio.funcs->get_memsize(adev); in soc21_get_config_memsize()
167 static u32 soc21_get_xclk(struct amdgpu_device *adev) in soc21_get_xclk() argument
169 return adev->clock.spll.reference_freq; in soc21_get_xclk()
173 void soc21_grbm_select(struct amdgpu_device *adev, in soc21_grbm_select() argument
185 static void soc21_vga_set_state(struct amdgpu_device *adev, bool state) in soc21_vga_set_state() argument
190 static bool soc21_read_disabled_bios(struct amdgpu_device *adev) in soc21_read_disabled_bios() argument
218 static uint32_t soc21_read_indexed_register(struct amdgpu_device *adev, u32 se_num, in soc21_read_indexed_register() argument
223 mutex_lock(&adev->grbm_idx_mutex); in soc21_read_indexed_register()
225 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); in soc21_read_indexed_register()
230 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); in soc21_read_indexed_register()
231 mutex_unlock(&adev->grbm_idx_mutex); in soc21_read_indexed_register()
235 static uint32_t soc21_get_register_value(struct amdgpu_device *adev, in soc21_get_register_value() argument
240 return soc21_read_indexed_register(adev, se_num, sh_num, reg_offset); in soc21_get_register_value()
242 if (reg_offset == SOC15_REG_OFFSET(GC, 0, regGB_ADDR_CONFIG) && adev->gfx.config.gb_addr_config) in soc21_get_register_value()
243 return adev->gfx.config.gb_addr_config; in soc21_get_register_value()
248 static int soc21_read_register(struct amdgpu_device *adev, u32 se_num, in soc21_read_register() argument
257 if (adev->reg_offset[en->hwip][en->inst] && in soc21_read_register()
258 reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg] in soc21_read_register()
262 *value = soc21_get_register_value(adev, in soc21_read_register()
271 static int soc21_asic_mode1_reset(struct amdgpu_device *adev)
276 amdgpu_atombios_scratch_regs_engine_hung(adev, true);
279 pci_clear_master(adev->pdev);
281 amdgpu_device_cache_pci_state(adev->pdev);
283 if (amdgpu_dpm_is_mode1_reset_supported(adev)) {
284 dev_info(adev->dev, "GPU smu mode1 reset\n");
285 ret = amdgpu_dpm_mode1_reset(adev);
287 dev_info(adev->dev, "GPU psp mode1 reset\n");
288 ret = psp_gpu_reset(adev);
292 dev_err(adev->dev, "GPU mode1 reset failed\n");
293 amdgpu_device_load_pci_state(adev->pdev);
296 for (i = 0; i < adev->usec_timeout; i++) {
297 u32 memsize = adev->nbio.funcs->get_memsize(adev);
304 amdgpu_atombios_scratch_regs_engine_hung(adev, false);
311 soc21_asic_reset_method(struct amdgpu_device *adev) in soc21_asic_reset_method() argument
319 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n", in soc21_asic_reset_method()
322 switch (adev->ip_versions[MP1_HWIP][0]) { in soc21_asic_reset_method()
329 if (amdgpu_dpm_is_baco_supported(adev)) in soc21_asic_reset_method()
336 static int soc21_asic_reset(struct amdgpu_device *adev) in soc21_asic_reset() argument
340 switch (soc21_asic_reset_method(adev)) { in soc21_asic_reset()
342 dev_info(adev->dev, "PCI reset\n"); in soc21_asic_reset()
343 ret = amdgpu_device_pci_reset(adev); in soc21_asic_reset()
346 dev_info(adev->dev, "BACO reset\n"); in soc21_asic_reset()
347 ret = amdgpu_dpm_baco_reset(adev); in soc21_asic_reset()
350 dev_info(adev->dev, "MODE2 reset\n"); in soc21_asic_reset()
351 ret = amdgpu_dpm_mode2_reset(adev); in soc21_asic_reset()
354 dev_info(adev->dev, "MODE1 reset\n"); in soc21_asic_reset()
355 ret = amdgpu_device_mode1_reset(adev); in soc21_asic_reset()
362 static int soc21_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) in soc21_set_uvd_clocks() argument
368 static int soc21_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) in soc21_set_vce_clocks() argument
374 static void soc21_pcie_gen3_enable(struct amdgpu_device *adev) in soc21_pcie_gen3_enable() argument
376 if (pci_is_root_bus(adev->pdev->bus)) in soc21_pcie_gen3_enable()
382 if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 | in soc21_pcie_gen3_enable()
389 static void soc21_program_aspm(struct amdgpu_device *adev) in soc21_program_aspm() argument
391 if (!amdgpu_device_should_use_aspm(adev)) in soc21_program_aspm()
394 if (!(adev->flags & AMD_IS_APU) && in soc21_program_aspm()
395 (adev->nbio.funcs->program_aspm)) in soc21_program_aspm()
396 adev->nbio.funcs->program_aspm(adev); in soc21_program_aspm()
399 static void soc21_enable_doorbell_aperture(struct amdgpu_device *adev, in soc21_enable_doorbell_aperture() argument
402 adev->nbio.funcs->enable_doorbell_aperture(adev, enable); in soc21_enable_doorbell_aperture()
403 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, enable); in soc21_enable_doorbell_aperture()
415 static uint32_t soc21_get_rev_id(struct amdgpu_device *adev) in soc21_get_rev_id() argument
417 return adev->nbio.funcs->get_rev_id(adev); in soc21_get_rev_id()
420 static bool soc21_need_full_reset(struct amdgpu_device *adev) in soc21_need_full_reset() argument
422 switch (adev->ip_versions[GC_HWIP][0]) { in soc21_need_full_reset()
424 return amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC); in soc21_need_full_reset()
433 static bool soc21_need_reset_on_init(struct amdgpu_device *adev) in soc21_need_reset_on_init() argument
437 if (adev->flags & AMD_IS_APU) in soc21_need_reset_on_init()
450 static uint64_t soc21_get_pcie_replay_count(struct amdgpu_device *adev) in soc21_get_pcie_replay_count() argument
460 static void soc21_init_doorbell_index(struct amdgpu_device *adev) in soc21_init_doorbell_index() argument
462 adev->doorbell_index.kiq = AMDGPU_NAVI10_DOORBELL_KIQ; in soc21_init_doorbell_index()
463 adev->doorbell_index.mec_ring0 = AMDGPU_NAVI10_DOORBELL_MEC_RING0; in soc21_init_doorbell_index()
464 adev->doorbell_index.mec_ring1 = AMDGPU_NAVI10_DOORBELL_MEC_RING1; in soc21_init_doorbell_index()
465 adev->doorbell_index.mec_ring2 = AMDGPU_NAVI10_DOORBELL_MEC_RING2; in soc21_init_doorbell_index()
466 adev->doorbell_index.mec_ring3 = AMDGPU_NAVI10_DOORBELL_MEC_RING3; in soc21_init_doorbell_index()
467 adev->doorbell_index.mec_ring4 = AMDGPU_NAVI10_DOORBELL_MEC_RING4; in soc21_init_doorbell_index()
468 adev->doorbell_index.mec_ring5 = AMDGPU_NAVI10_DOORBELL_MEC_RING5; in soc21_init_doorbell_index()
469 adev->doorbell_index.mec_ring6 = AMDGPU_NAVI10_DOORBELL_MEC_RING6; in soc21_init_doorbell_index()
470 adev->doorbell_index.mec_ring7 = AMDGPU_NAVI10_DOORBELL_MEC_RING7; in soc21_init_doorbell_index()
471 adev->doorbell_index.userqueue_start = AMDGPU_NAVI10_DOORBELL_USERQUEUE_START; in soc21_init_doorbell_index()
472 adev->doorbell_index.userqueue_end = AMDGPU_NAVI10_DOORBELL_USERQUEUE_END; in soc21_init_doorbell_index()
473 adev->doorbell_index.gfx_ring0 = AMDGPU_NAVI10_DOORBELL_GFX_RING0; in soc21_init_doorbell_index()
474 adev->doorbell_index.gfx_ring1 = AMDGPU_NAVI10_DOORBELL_GFX_RING1; in soc21_init_doorbell_index()
475 adev->doorbell_index.gfx_userqueue_start = in soc21_init_doorbell_index()
477 adev->doorbell_index.gfx_userqueue_end = in soc21_init_doorbell_index()
479 adev->doorbell_index.mes_ring0 = AMDGPU_NAVI10_DOORBELL_MES_RING0; in soc21_init_doorbell_index()
480 adev->doorbell_index.mes_ring1 = AMDGPU_NAVI10_DOORBELL_MES_RING1; in soc21_init_doorbell_index()
481 adev->doorbell_index.sdma_engine[0] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0; in soc21_init_doorbell_index()
482 adev->doorbell_index.sdma_engine[1] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1; in soc21_init_doorbell_index()
483 adev->doorbell_index.ih = AMDGPU_NAVI10_DOORBELL_IH; in soc21_init_doorbell_index()
484 adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_NAVI10_DOORBELL64_VCN0_1; in soc21_init_doorbell_index()
485 adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_NAVI10_DOORBELL64_VCN2_3; in soc21_init_doorbell_index()
486 adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_NAVI10_DOORBELL64_VCN4_5; in soc21_init_doorbell_index()
487 adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_NAVI10_DOORBELL64_VCN6_7; in soc21_init_doorbell_index()
488 adev->doorbell_index.first_non_cp = AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP; in soc21_init_doorbell_index()
489 adev->doorbell_index.last_non_cp = AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP; in soc21_init_doorbell_index()
491 adev->doorbell_index.max_assignment = AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT << 1; in soc21_init_doorbell_index()
492 adev->doorbell_index.sdma_doorbell_range = 20; in soc21_init_doorbell_index()
495 static void soc21_pre_asic_init(struct amdgpu_device *adev) in soc21_pre_asic_init() argument
499 static int soc21_update_umd_stable_pstate(struct amdgpu_device *adev, in soc21_update_umd_stable_pstate() argument
503 amdgpu_gfx_rlc_enter_safe_mode(adev); in soc21_update_umd_stable_pstate()
505 amdgpu_gfx_rlc_exit_safe_mode(adev); in soc21_update_umd_stable_pstate()
507 if (adev->gfx.funcs->update_perfmon_mgcg) in soc21_update_umd_stable_pstate()
508 adev->gfx.funcs->update_perfmon_mgcg(adev, !enter); in soc21_update_umd_stable_pstate()
538 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in soc21_common_early_init() local
540 adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET; in soc21_common_early_init()
541 adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET; in soc21_common_early_init()
542 adev->smc_rreg = NULL; in soc21_common_early_init()
543 adev->smc_wreg = NULL; in soc21_common_early_init()
544 adev->pcie_rreg = &soc21_pcie_rreg; in soc21_common_early_init()
545 adev->pcie_wreg = &soc21_pcie_wreg; in soc21_common_early_init()
546 adev->pcie_rreg64 = &soc21_pcie_rreg64; in soc21_common_early_init()
547 adev->pcie_wreg64 = &soc21_pcie_wreg64; in soc21_common_early_init()
548 adev->pciep_rreg = amdgpu_device_pcie_port_rreg; in soc21_common_early_init()
549 adev->pciep_wreg = amdgpu_device_pcie_port_wreg; in soc21_common_early_init()
552 adev->uvd_ctx_rreg = NULL; in soc21_common_early_init()
553 adev->uvd_ctx_wreg = NULL; in soc21_common_early_init()
555 adev->didt_rreg = &soc21_didt_rreg; in soc21_common_early_init()
556 adev->didt_wreg = &soc21_didt_wreg; in soc21_common_early_init()
558 adev->asic_funcs = &soc21_asic_funcs; in soc21_common_early_init()
560 adev->rev_id = soc21_get_rev_id(adev); in soc21_common_early_init()
561 adev->external_rev_id = 0xff; in soc21_common_early_init()
562 switch (adev->ip_versions[GC_HWIP][0]) { in soc21_common_early_init()
564 adev->cg_flags = AMD_CG_SUPPORT_GFX_CGCG | in soc21_common_early_init()
582 adev->pg_flags = AMD_PG_SUPPORT_VCN | in soc21_common_early_init()
587 if (amdgpu_sriov_vf(adev)) { in soc21_common_early_init()
588 adev->cg_flags = 0; in soc21_common_early_init()
589 adev->pg_flags = 0; in soc21_common_early_init()
591 adev->external_rev_id = adev->rev_id + 0x1; // TODO: need update in soc21_common_early_init()
594 adev->cg_flags = in soc21_common_early_init()
604 adev->pg_flags = in soc21_common_early_init()
610 adev->external_rev_id = adev->rev_id + 0x10; in soc21_common_early_init()
613 adev->cg_flags = in soc21_common_early_init()
631 adev->pg_flags = in soc21_common_early_init()
636 adev->external_rev_id = adev->rev_id + 0x1; in soc21_common_early_init()
639 adev->cg_flags = AMD_CG_SUPPORT_VCN_MGCG | in soc21_common_early_init()
645 adev->pg_flags = AMD_PG_SUPPORT_VCN | in soc21_common_early_init()
648 if (amdgpu_sriov_vf(adev)) { in soc21_common_early_init()
650 adev->cg_flags = 0; in soc21_common_early_init()
651 adev->pg_flags = 0; in soc21_common_early_init()
653 adev->external_rev_id = adev->rev_id + 0x20; in soc21_common_early_init()
680 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in soc21_common_hw_init() local
683 soc21_pcie_gen3_enable(adev); in soc21_common_hw_init()
685 soc21_program_aspm(adev); in soc21_common_hw_init()
687 adev->nbio.funcs->init_registers(adev); in soc21_common_hw_init()
692 if (adev->nbio.funcs->remap_hdp_registers) in soc21_common_hw_init()
693 adev->nbio.funcs->remap_hdp_registers(adev); in soc21_common_hw_init()
695 soc21_enable_doorbell_aperture(adev, true); in soc21_common_hw_init()
702 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in soc21_common_hw_fini() local
705 soc21_enable_doorbell_aperture(adev, false); in soc21_common_hw_fini()
712 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in soc21_common_suspend() local
714 return soc21_common_hw_fini(adev); in soc21_common_suspend()
719 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in soc21_common_resume() local
721 return soc21_common_hw_init(adev); in soc21_common_resume()
742 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in soc21_common_set_clockgating_state() local
744 switch (adev->ip_versions[NBIO_HWIP][0]) { in soc21_common_set_clockgating_state()
748 adev->nbio.funcs->update_medium_grain_clock_gating(adev, in soc21_common_set_clockgating_state()
750 adev->nbio.funcs->update_medium_grain_light_sleep(adev, in soc21_common_set_clockgating_state()
752 adev->hdp.funcs->update_clock_gating(adev, in soc21_common_set_clockgating_state()
764 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in soc21_common_set_powergating_state() local
766 switch (adev->ip_versions[LSDMA_HWIP][0]) { in soc21_common_set_powergating_state()
769 adev->lsdma.funcs->update_memory_power_gating(adev, in soc21_common_set_powergating_state()
781 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in soc21_common_get_clockgating_state() local
783 adev->nbio.funcs->get_clockgating_state(adev, flags); in soc21_common_get_clockgating_state()
785 adev->hdp.funcs->get_clock_gating_state(adev, flags); in soc21_common_get_clockgating_state()