Lines Matching +full:3 +full:- +full:31
35 #define PACKET_TYPE3 3
37 #define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3)
59 #define PACKETJ_CONDITION_CHECK3 3
68 #define PACKETJ_TYPE3 3
79 /* Packet 3 types */
83 #define CE_PARTITION_BASE 3
111 /* 0 - register
112 * 1 - memory (sync - via GRBM)
113 * 2 - gl2
114 * 3 - gds
115 * 4 - reserved
116 * 5 - memory (async - direct)
121 /* 0 - LRU
122 * 1 - Stream
125 /* 0 - me
126 * 1 - pfp
127 * 2 - ce
137 /* 0 - always
138 * 1 - <
139 * 2 - <=
140 * 3 - ==
141 * 4 - !=
142 * 5 - >=
143 * 6 - >
146 /* 0 - reg
147 * 1 - mem
150 /* 0 - wait_reg_mem
151 * 1 - wr_wait_wr_reg
154 /* 0 - me
155 * 1 - pfp
160 /* 0 - LRU
161 * 1 - Stream
162 * 2 - Bypass
171 /* 0 - any non-TS event
172 * 1 - ZPASS_DONE, PIXEL_PIPE_STAT_*
173 * 2 - SAMPLE_PIPELINESTAT
174 * 3 - SAMPLE_STREAMOUTSTAT*
175 * 4 - *S_PARTIAL_FLUSH
189 /* 0 - discard
190 * 1 - send low 32bit data
191 * 2 - send 64bit data
192 * 3 - send 64bit GPU counter value
193 * 4 - send 64bit sys counter value
196 /* 0 - none
197 * 1 - interrupt only (DATA_SEL = 0)
198 * 2 - interrupt when data write is confirmed
201 /* 0 - MC
202 * 1 - TC/L2
209 # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28)
213 * 3. SRC_ADDR_LO or DATA [31:0]
214 * 4. SRC_ADDR_HI [31:0]
215 * 5. DST_ADDR_LO [31:0]
221 /* 0 - ME
222 * 1 - PFP
225 /* 0 - LRU
226 * 1 - Stream
229 /* 0 - DST_ADDR using DAS
230 * 1 - GDS
231 * 3 - DST_ADDR using L2
234 /* 0 - LRU
235 * 1 - Stream
238 /* 0 - SRC_ADDR using SAS
239 * 1 - GDS
240 * 2 - DATA
241 * 3 - SRC_ADDR using L2
243 # define PACKET3_DMA_DATA_CP_SYNC (1 << 31)
246 /* 0 - memory
247 * 1 - register
250 /* 0 - memory
251 * 1 - register
259 * 2.1 ENGINE_SEL [31:31]
260 * 3. COHER_SIZE [31:0]
262 * 5. COHER_BASE_LO [31:0]
267 #define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_NC_ACTION_ENA(x) ((x) << 3)
327 * 3. QUEUE_MASK_LO [31:0]
328 * 4. QUEUE_MASK_HI [31:0]
329 * 5. GWS_MASK_LO [31:0]
330 * 6. GWS_MASK_HI [31:0]
340 * 3. CONTROL2
341 * 4. MQD_ADDR_LO [31:0]
342 * 5. MQD_ADDR_HI [31:0]
343 * 6. WPTR_ADDR_LO [31:0]
344 * 7. WPTR_ADDR_HI [31:0]
362 * 3. CONTROL2
369 /* 0 - PREEMPT_QUEUES
370 * 1 - RESET_QUEUES
371 * 2 - DISABLE_PROCESS_QUEUES
372 * 3 - PREEMPT_QUEUES_NO_UNMAP
392 * 3. CONTROL2
393 * 4. ADDR_LO [31:0]
394 * 5. ADDR_HI [31:0]
395 * 6. DATA_LO [31:0]
396 * 7. DATA_HI [31:0]