28 #define SOC15_REG_OFFSET(ip, inst, reg)	(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg)  argument
30 #define __WREG32_SOC15_RLC__(reg, value, flag, hwip) \  argument
32 	 amdgpu_sriov_wreg(adev, reg, value, flag, hwip) : \
33 	 WREG32(reg, value))
35 #define __RREG32_SOC15_RLC__(reg, flag, hwip) \  argument
37 	 amdgpu_sriov_rreg(adev, reg, flag, hwip) : \
38 	 RREG32(reg))
40 #define WREG32_FIELD15(ip, idx, reg, field, val)	\  argument
41 	 __WREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg,	\
43 					adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg, \
45 				~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field), \
49 …__WREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][idx][reg##reg_name##_BASE_IDX] + reg##reg_name,  …
51 					adev->reg_offset[ip##_HWIP][idx][reg##reg_name##_BASE_IDX] + reg##reg_name, \
56 #define RREG32_SOC15(ip, inst, reg) \  argument
57 	__RREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg, \
60 #define RREG32_SOC15_IP(ip, reg) __RREG32_SOC15_RLC__(reg, 0, ip##_HWIP)  argument
62 #define RREG32_SOC15_IP_NO_KIQ(ip, reg) __RREG32_SOC15_RLC__(reg, AMDGPU_REGS_NO_KIQ, ip##_HWIP)  argument
64 #define RREG32_SOC15_NO_KIQ(ip, inst, reg) \  argument
65 	__RREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg, \
68 #define RREG32_SOC15_OFFSET(ip, inst, reg, offset) \  argument
69 …__RREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset, 0, ip##_H…
71 #define WREG32_SOC15(ip, inst, reg, value) \  argument
72 	 __WREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg), \
75 #define WREG32_SOC15_IP(ip, reg, value) \  argument
76 	 __WREG32_SOC15_RLC__(reg, value, 0, ip##_HWIP)
78 #define WREG32_SOC15_IP_NO_KIQ(ip, reg, value) \  argument
79 	 __WREG32_SOC15_RLC__(reg, value, AMDGPU_REGS_NO_KIQ, ip##_HWIP)
81 #define WREG32_SOC15_NO_KIQ(ip, inst, reg, value) \  argument
82 	__WREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg, \
85 #define WREG32_SOC15_OFFSET(ip, inst, reg, offset, value) \  argument
86 	 __WREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset, \
89 #define SOC15_WAIT_ON_RREG(ip, inst, reg, expected_value, mask) \  argument
93 		uint32_t tmp_ = RREG32(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg); \
102 			tmp_ = RREG32(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg); \
106 					  inst, #reg, (unsigned)expected_value, (unsigned)(tmp_ & (mask))); \
115 #define WREG32_RLC(reg, value) \  argument
116 	__WREG32_SOC15_RLC__(reg, value, AMDGPU_REGS_RLC, GC_HWIP)
118 #define WREG32_RLC_EX(prefix, reg, value) \  argument
127 			WREG32(r1, (reg | 0x80000000));	\
136 				pr_err("timeout: rlcg program reg:0x%05x failed !\n", reg);	\
138 			WREG32(reg, value); \
143 #define WREG32_SOC15_RLC_SHADOW(ip, inst, reg, value) \  argument
144 …__WREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg), value, AMDGPU_REGS…
147 #define RREG32_RLC(reg) \  argument
148 	__RREG32_SOC15_RLC__(reg, AMDGPU_REGS_RLC, GC_HWIP)
150 #define WREG32_RLC_NO_KIQ(reg, value, hwip) \  argument
151 	__WREG32_SOC15_RLC__(reg, value, AMDGPU_REGS_NO_KIQ | AMDGPU_REGS_RLC, hwip)
153 #define RREG32_RLC_NO_KIQ(reg, hwip) \  argument
154 	__RREG32_SOC15_RLC__(reg, AMDGPU_REGS_NO_KIQ | AMDGPU_REGS_RLC, hwip)
156 #define WREG32_SOC15_RLC_SHADOW_EX(prefix, ip, inst, reg, value) \  argument
158 		uint32_t target_reg = adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg;\
174 #define RREG32_SOC15_RLC(ip, inst, reg) \  argument
175 …__RREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg, AMDGPU_REGS_RLC, ip#…
177 #define WREG32_SOC15_RLC(ip, inst, reg, value) \  argument
179 		uint32_t target_reg = adev->reg_offset[ip##_HWIP][0][reg##_BASE_IDX] + reg;\
183 #define WREG32_SOC15_RLC_EX(prefix, ip, inst, reg, value) \  argument
185 			uint32_t target_reg = adev->reg_offset[GC_HWIP][0][reg##_BASE_IDX] + reg;\
189 #define WREG32_FIELD15_RLC(ip, idx, reg, field, val)   \  argument
190 	__WREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg), \
191 			     (__RREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg, \
193 			      ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field), \
196 #define WREG32_SOC15_OFFSET_RLC(ip, inst, reg, offset, value) \  argument
197 …__WREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset, value, AM…
199 #define RREG32_SOC15_OFFSET_RLC(ip, inst, reg, offset) \  argument
200 …__RREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset, AMDGPU_RE…