Lines Matching refs:ih
44 adev->irq.ih.enabled = true; in si_ih_enable_interrupts()
58 adev->irq.ih.enabled = false; in si_ih_disable_interrupts()
59 adev->irq.ih.rptr = 0; in si_ih_disable_interrupts()
64 struct amdgpu_ih_ring *ih = &adev->irq.ih; in si_ih_irq_init() local
76 WREG32(IH_RB_BASE, adev->irq.ih.gpu_addr >> 8); in si_ih_irq_init()
77 rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4); in si_ih_irq_init()
84 WREG32(IH_RB_WPTR_ADDR_LO, lower_32_bits(ih->wptr_addr)); in si_ih_irq_init()
85 WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(ih->wptr_addr) & 0xFF); in si_ih_irq_init()
108 struct amdgpu_ih_ring *ih) in si_ih_get_wptr() argument
112 wptr = le32_to_cpu(*ih->wptr_cpu); in si_ih_get_wptr()
117 wptr, ih->rptr, (wptr + 16) & ih->ptr_mask); in si_ih_get_wptr()
118 ih->rptr = (wptr + 16) & ih->ptr_mask; in si_ih_get_wptr()
123 return (wptr & ih->ptr_mask); in si_ih_get_wptr()
127 struct amdgpu_ih_ring *ih, in si_ih_decode_iv() argument
130 u32 ring_index = ih->rptr >> 2; in si_ih_decode_iv()
133 dw[0] = le32_to_cpu(ih->ring[ring_index + 0]); in si_ih_decode_iv()
134 dw[1] = le32_to_cpu(ih->ring[ring_index + 1]); in si_ih_decode_iv()
135 dw[2] = le32_to_cpu(ih->ring[ring_index + 2]); in si_ih_decode_iv()
136 dw[3] = le32_to_cpu(ih->ring[ring_index + 3]); in si_ih_decode_iv()
144 ih->rptr += 16; in si_ih_decode_iv()
148 struct amdgpu_ih_ring *ih) in si_ih_set_rptr() argument
150 WREG32(IH_RB_RPTR, ih->rptr); in si_ih_set_rptr()
167 r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 64 * 1024, false); in si_ih_sw_init()