sdma_v6_0.c - OpenGrok cross reference for /Linux-v6.1/drivers/gpu/drm/amd/amdgpu/sdma_v6

Lines Matching refs:GC
236 			WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev,  in sdma_v6_0_ring_set_wptr()
239 			WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev,  in sdma_v6_0_ring_set_wptr()
407 		rb_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL));  in sdma_v6_0_gfx_stop()
409 		WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl);  in sdma_v6_0_gfx_stop()
410 		ib_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL));  in sdma_v6_0_gfx_stop()
412 		WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL), ib_cntl);  in sdma_v6_0_gfx_stop()
459 		f32_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL));  in sdma_v6_0_enable()
461 		WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL), f32_cntl);  in sdma_v6_0_enable()
488 			WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0);  in sdma_v6_0_gfx_resume()
492 		rb_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL));  in sdma_v6_0_gfx_resume()
500 		WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl);  in sdma_v6_0_gfx_resume()
503 		WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR), 0);  in sdma_v6_0_gfx_resume()
504 		WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_HI), 0);  in sdma_v6_0_gfx_resume()
505 		WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR), 0);  in sdma_v6_0_gfx_resume()
506 		WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_HI), 0);  in sdma_v6_0_gfx_resume()
510 		WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_LO),  in sdma_v6_0_gfx_resume()
512 		WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_HI),  in sdma_v6_0_gfx_resume()
516 		WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_ADDR_HI),  in sdma_v6_0_gfx_resume()
518 		WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_ADDR_LO),  in sdma_v6_0_gfx_resume()
528 …WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_BASE), ring->gpu_addr >> …  in sdma_v6_0_gfx_resume()
529 …WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_BASE_HI), ring->gpu_addr …  in sdma_v6_0_gfx_resume()
534 		WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_MINOR_PTR_UPDATE), 1);  in sdma_v6_0_gfx_resume()
537 …WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR), lower_32_bits(ring…  in sdma_v6_0_gfx_resume()
538 …WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_HI), upper_32_bits(r…  in sdma_v6_0_gfx_resume()
541 		doorbell = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL));  in sdma_v6_0_gfx_resume()
542 …doorbell_offset = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL_O…  in sdma_v6_0_gfx_resume()
551 		WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL), doorbell);  in sdma_v6_0_gfx_resume()
552 …WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL_OFFSET), doorbell_o…  in sdma_v6_0_gfx_resume()
563 		WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_MINOR_PTR_UPDATE), 0);  in sdma_v6_0_gfx_resume()
566 		temp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_CNTL));  in sdma_v6_0_gfx_resume()
569 		WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_CNTL), temp);  in sdma_v6_0_gfx_resume()
572 		temp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_PAGE));  in sdma_v6_0_gfx_resume()
578 		WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_PAGE), temp);  in sdma_v6_0_gfx_resume()
582 			temp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL));  in sdma_v6_0_gfx_resume()
585 			WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL), temp);  in sdma_v6_0_gfx_resume()
590 		WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl);  in sdma_v6_0_gfx_resume()
592 		ib_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL));  in sdma_v6_0_gfx_resume()
598 		WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL), ib_cntl);  in sdma_v6_0_gfx_resume()
744 		tmp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_FREEZE));  in sdma_v6_0_soft_reset()
746 		WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_FREEZE), tmp);  in sdma_v6_0_soft_reset()
747 		tmp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL));  in sdma_v6_0_soft_reset()
750 		WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL), tmp);  in sdma_v6_0_soft_reset()
752 		WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_PREEMPT), 0);  in sdma_v6_0_soft_reset()
757 		WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, tmp);  in sdma_v6_0_soft_reset()
758 		tmp = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET);  in sdma_v6_0_soft_reset()
762 		WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, 0);  in sdma_v6_0_soft_reset()
763 		tmp = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET);  in sdma_v6_0_soft_reset()
856 	m->sdmax_rlcx_ib_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, 0,  in sdma_v6_0_mqd_init()