267 	for (i = 0; i < adev->sdma.num_instances; i++) {  in sdma_v5_0_init_microcode()
429 	struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);  in sdma_v5_0_ring_insert_nop()  local
433 		if (sdma && sdma->burst_nop && (i == 0))  in sdma_v5_0_ring_insert_nop()
592 	for (i = 0; i < adev->sdma.num_instances; i++) {  in sdma_v5_0_gfx_stop()
651 	for (i = 0; i < adev->sdma.num_instances; i++) {  in sdma_v5_0_ctx_switch_enable()
693 	for (i = 0; i < adev->sdma.num_instances; i++) {  in sdma_v5_0_enable()
720 	for (i = 0; i < adev->sdma.num_instances; i++) {  in sdma_v5_0_gfx_resume()
721 		ring = &adev->sdma.instance[i].ring;  in sdma_v5_0_gfx_resume()
897 	for (i = 0; i < adev->sdma.num_instances; i++) {  in sdma_v5_0_load_microcode()
898 		if (!adev->sdma.instance[i].fw)  in sdma_v5_0_load_microcode()
901 		hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;  in sdma_v5_0_load_microcode()
906 			(adev->sdma.instance[i].fw->data +  in sdma_v5_0_load_microcode()
917 		WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), adev->sdma.instance[i].fw_version);  in sdma_v5_0_load_microcode()
1275 	struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);  in sdma_v5_0_ring_pad_ib()  local
1281 		if (sdma && sdma->burst_nop && (i == 0))  in sdma_v5_0_ring_pad_ib()
1389 			      &adev->sdma.trap_irq);  in sdma_v5_0_sw_init()
1396 			      &adev->sdma.trap_irq);  in sdma_v5_0_sw_init()
1406 	for (i = 0; i < adev->sdma.num_instances; i++) {  in sdma_v5_0_sw_init()
1407 		ring = &adev->sdma.instance[i].ring;  in sdma_v5_0_sw_init()
1419 		r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq,  in sdma_v5_0_sw_init()
1435 	for (i = 0; i < adev->sdma.num_instances; i++)  in sdma_v5_0_sw_fini()
1436 		amdgpu_ring_fini(&adev->sdma.instance[i].ring);  in sdma_v5_0_sw_fini()
1490 	for (i = 0; i < adev->sdma.num_instances; i++) {  in sdma_v5_0_is_idle()
1619 			amdgpu_fence_process(&adev->sdma.instance[0].ring);  in sdma_v5_0_process_trap_irq()
1635 			amdgpu_fence_process(&adev->sdma.instance[1].ring);  in sdma_v5_0_process_trap_irq()
1665 	for (i = 0; i < adev->sdma.num_instances; i++) {  in sdma_v5_0_update_medium_grain_clock_gating()
1702 	for (i = 0; i < adev->sdma.num_instances; i++) {  in sdma_v5_0_update_medium_grain_light_sleep()
1830 	for (i = 0; i < adev->sdma.num_instances; i++) {  in sdma_v5_0_set_ring_funcs()
1831 		adev->sdma.instance[i].ring.funcs = &sdma_v5_0_ring_funcs;  in sdma_v5_0_set_ring_funcs()
1832 		adev->sdma.instance[i].ring.me = i;  in sdma_v5_0_set_ring_funcs()
1847 	adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE0 +  in sdma_v5_0_set_irq_funcs()
1848 					adev->sdma.num_instances;  in sdma_v5_0_set_irq_funcs()
1849 	adev->sdma.trap_irq.funcs = &sdma_v5_0_trap_irq_funcs;  in sdma_v5_0_set_irq_funcs()
1850 	adev->sdma.illegal_inst_irq.funcs = &sdma_v5_0_illegal_inst_irq_funcs;  in sdma_v5_0_set_irq_funcs()
1919 		adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;  in sdma_v5_0_set_buffer_funcs()
1936 		for (i = 0; i < adev->sdma.num_instances; i++) {  in sdma_v5_0_set_vm_pte_funcs()
1938 				&adev->sdma.instance[i].ring.sched;  in sdma_v5_0_set_vm_pte_funcs()
1940 		adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;  in sdma_v5_0_set_vm_pte_funcs()