Lines Matching +full:3 +full:- +full:31
33 #define PACKET_TYPE3 3
35 #define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3)
54 /* Packet 3 types */
58 #define CE_PARTITION_BASE 3
90 /* 0 - register
91 * 1 - memory (sync - via GRBM)
92 * 2 - gl2
93 * 3 - gds
94 * 4 - reserved
95 * 5 - memory (async - direct)
100 /* 0 - LRU
101 * 1 - Stream
104 /* 0 - me
105 * 1 - pfp
106 * 2 - ce
118 /* 0 - always
119 * 1 - <
120 * 2 - <=
121 * 3 - ==
122 * 4 - !=
123 * 5 - >=
124 * 6 - >
127 /* 0 - reg
128 * 1 - mem
131 /* 0 - wait_reg_mem
132 * 1 - wr_wait_wr_reg
135 /* 0 - me
136 * 1 - pfp
141 /* 0 - LRU
142 * 1 - Stream
143 * 2 - Bypass
157 /* 0 - any non-TS event
158 * 1 - ZPASS_DONE, PIXEL_PIPE_STAT_*
159 * 2 - SAMPLE_PIPELINESTAT
160 * 3 - SAMPLE_STREAMOUTSTAT*
161 * 4 - *S_PARTIAL_FLUSH
179 /* 0 - cache_policy__me_release_mem__lru
180 * 1 - cache_policy__me_release_mem__stream
181 * 2 - cache_policy__me_release_mem__noa
182 * 3 - cache_policy__me_release_mem__bypass
187 /* 0 - discard
188 * 1 - send low 32bit data
189 * 2 - send 64bit data
190 * 3 - send 64bit GPU counter value
191 * 4 - send 64bit sys counter value
194 /* 0 - none
195 * 1 - interrupt only (DATA_SEL = 0)
196 * 2 - interrupt when data write is confirmed
199 /* 0 - MC
200 * 1 - TC/L2
207 # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28)
211 * 3. SRC_ADDR_LO or DATA [31:0]
212 * 4. SRC_ADDR_HI [31:0]
213 * 5. DST_ADDR_LO [31:0]
215 * 7. COMMAND [31:26] | BYTE_COUNT [25:0]
219 /* 0 - ME
220 * 1 - PFP
223 /* 0 - LRU
224 * 1 - Stream
227 /* 0 - DST_ADDR using DAS
228 * 1 - GDS
229 * 3 - DST_ADDR using L2
232 /* 0 - LRU
233 * 1 - Stream
236 /* 0 - SRC_ADDR using SAS
237 * 1 - GDS
238 * 2 - DATA
239 * 3 - SRC_ADDR using L2
241 # define PACKET3_DMA_DATA_CP_SYNC (1 << 31)
244 /* 0 - memory
245 * 1 - register
248 /* 0 - memory
249 * 1 - register
261 * 2.1 ENGINE_SEL [31:31]
262 * 2. COHER_SIZE [31:0]
263 * 3. COHER_SIZE_HI [7:0]
264 * 4. COHER_BASE_LO [31:0]
274 * 3:FIRST_LAST
281 * 3:FIRST_LAST
295 * 3:FIRST_LAST
382 * 3. QUEUE_MASK_LO [31:0]
383 * 4. QUEUE_MASK_HI [31:0]
384 * 5. GWS_MASK_LO [31:0]
385 * 6. GWS_MASK_HI [31:0]
396 * 3. CONTROL2
397 * 4. MQD_ADDR_LO [31:0]
398 * 5. MQD_ADDR_HI [31:0]
399 * 6. WPTR_ADDR_LO [31:0]
400 * 7. WPTR_ADDR_HI [31:0]
418 * 3. CONTROL2
425 /* 0 - PREEMPT_QUEUES
426 * 1 - RESET_QUEUES
427 * 2 - DISABLE_PROCESS_QUEUES
428 * 3 - PREEMPT_QUEUES_NO_UNMAP
448 * 3. CONTROL2
449 * 4. ADDR_LO [31:0]
450 * 5. ADDR_HI [31:0]
451 * 6. DATA_LO [31:0]
452 * 7. DATA_HI [31:0]