Lines Matching refs:adev
181 static int nv_query_video_codecs(struct amdgpu_device *adev, bool encode, in nv_query_video_codecs() argument
184 switch (adev->ip_versions[UVD_HWIP][0]) { in nv_query_video_codecs()
188 if (amdgpu_sriov_vf(adev)) { in nv_query_video_codecs()
235 static u32 nv_pcie_rreg(struct amdgpu_device *adev, u32 reg) in nv_pcie_rreg() argument
238 address = adev->nbio.funcs->get_pcie_index_offset(adev); in nv_pcie_rreg()
239 data = adev->nbio.funcs->get_pcie_data_offset(adev); in nv_pcie_rreg()
241 return amdgpu_device_indirect_rreg(adev, address, data, reg); in nv_pcie_rreg()
244 static void nv_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v) in nv_pcie_wreg() argument
248 address = adev->nbio.funcs->get_pcie_index_offset(adev); in nv_pcie_wreg()
249 data = adev->nbio.funcs->get_pcie_data_offset(adev); in nv_pcie_wreg()
251 amdgpu_device_indirect_wreg(adev, address, data, reg, v); in nv_pcie_wreg()
254 static u64 nv_pcie_rreg64(struct amdgpu_device *adev, u32 reg) in nv_pcie_rreg64() argument
257 address = adev->nbio.funcs->get_pcie_index_offset(adev); in nv_pcie_rreg64()
258 data = adev->nbio.funcs->get_pcie_data_offset(adev); in nv_pcie_rreg64()
260 return amdgpu_device_indirect_rreg64(adev, address, data, reg); in nv_pcie_rreg64()
263 static void nv_pcie_wreg64(struct amdgpu_device *adev, u32 reg, u64 v) in nv_pcie_wreg64() argument
267 address = adev->nbio.funcs->get_pcie_index_offset(adev); in nv_pcie_wreg64()
268 data = adev->nbio.funcs->get_pcie_data_offset(adev); in nv_pcie_wreg64()
270 amdgpu_device_indirect_wreg64(adev, address, data, reg, v); in nv_pcie_wreg64()
273 static u32 nv_didt_rreg(struct amdgpu_device *adev, u32 reg) in nv_didt_rreg() argument
281 spin_lock_irqsave(&adev->didt_idx_lock, flags); in nv_didt_rreg()
284 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); in nv_didt_rreg()
288 static void nv_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) in nv_didt_wreg() argument
295 spin_lock_irqsave(&adev->didt_idx_lock, flags); in nv_didt_wreg()
298 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); in nv_didt_wreg()
301 static u32 nv_get_config_memsize(struct amdgpu_device *adev) in nv_get_config_memsize() argument
303 return adev->nbio.funcs->get_memsize(adev); in nv_get_config_memsize()
306 static u32 nv_get_xclk(struct amdgpu_device *adev) in nv_get_xclk() argument
308 return adev->clock.spll.reference_freq; in nv_get_xclk()
312 void nv_grbm_select(struct amdgpu_device *adev, in nv_grbm_select() argument
324 static void nv_vga_set_state(struct amdgpu_device *adev, bool state) in nv_vga_set_state() argument
329 static bool nv_read_disabled_bios(struct amdgpu_device *adev) in nv_read_disabled_bios() argument
357 static uint32_t nv_read_indexed_register(struct amdgpu_device *adev, u32 se_num, in nv_read_indexed_register() argument
362 mutex_lock(&adev->grbm_idx_mutex); in nv_read_indexed_register()
364 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); in nv_read_indexed_register()
369 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); in nv_read_indexed_register()
370 mutex_unlock(&adev->grbm_idx_mutex); in nv_read_indexed_register()
374 static uint32_t nv_get_register_value(struct amdgpu_device *adev, in nv_get_register_value() argument
379 return nv_read_indexed_register(adev, se_num, sh_num, reg_offset); in nv_get_register_value()
382 return adev->gfx.config.gb_addr_config; in nv_get_register_value()
387 static int nv_read_register(struct amdgpu_device *adev, u32 se_num, in nv_read_register() argument
396 if (adev->reg_offset[en->hwip][en->inst] && in nv_read_register()
397 reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg] in nv_read_register()
401 *value = nv_get_register_value(adev, in nv_read_register()
409 static int nv_asic_mode2_reset(struct amdgpu_device *adev) in nv_asic_mode2_reset() argument
414 amdgpu_atombios_scratch_regs_engine_hung(adev, true); in nv_asic_mode2_reset()
417 pci_clear_master(adev->pdev); in nv_asic_mode2_reset()
419 amdgpu_device_cache_pci_state(adev->pdev); in nv_asic_mode2_reset()
421 ret = amdgpu_dpm_mode2_reset(adev); in nv_asic_mode2_reset()
423 dev_err(adev->dev, "GPU mode2 reset failed\n"); in nv_asic_mode2_reset()
425 amdgpu_device_load_pci_state(adev->pdev); in nv_asic_mode2_reset()
428 for (i = 0; i < adev->usec_timeout; i++) { in nv_asic_mode2_reset()
429 u32 memsize = adev->nbio.funcs->get_memsize(adev); in nv_asic_mode2_reset()
436 amdgpu_atombios_scratch_regs_engine_hung(adev, false); in nv_asic_mode2_reset()
442 nv_asic_reset_method(struct amdgpu_device *adev) in nv_asic_reset_method() argument
451 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n", in nv_asic_reset_method()
454 switch (adev->ip_versions[MP1_HWIP][0]) { in nv_asic_reset_method()
467 if (amdgpu_dpm_is_baco_supported(adev)) in nv_asic_reset_method()
474 static int nv_asic_reset(struct amdgpu_device *adev) in nv_asic_reset() argument
478 switch (nv_asic_reset_method(adev)) { in nv_asic_reset()
480 dev_info(adev->dev, "PCI reset\n"); in nv_asic_reset()
481 ret = amdgpu_device_pci_reset(adev); in nv_asic_reset()
484 dev_info(adev->dev, "BACO reset\n"); in nv_asic_reset()
485 ret = amdgpu_dpm_baco_reset(adev); in nv_asic_reset()
488 dev_info(adev->dev, "MODE2 reset\n"); in nv_asic_reset()
489 ret = nv_asic_mode2_reset(adev); in nv_asic_reset()
492 dev_info(adev->dev, "MODE1 reset\n"); in nv_asic_reset()
493 ret = amdgpu_device_mode1_reset(adev); in nv_asic_reset()
500 static int nv_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) in nv_set_uvd_clocks() argument
506 static int nv_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) in nv_set_vce_clocks() argument
512 static void nv_pcie_gen3_enable(struct amdgpu_device *adev) in nv_pcie_gen3_enable() argument
514 if (pci_is_root_bus(adev->pdev->bus)) in nv_pcie_gen3_enable()
520 if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 | in nv_pcie_gen3_enable()
527 static void nv_program_aspm(struct amdgpu_device *adev) in nv_program_aspm() argument
529 if (!amdgpu_device_should_use_aspm(adev)) in nv_program_aspm()
532 if (!(adev->flags & AMD_IS_APU) && in nv_program_aspm()
533 (adev->nbio.funcs->program_aspm)) in nv_program_aspm()
534 adev->nbio.funcs->program_aspm(adev); in nv_program_aspm()
538 static void nv_enable_doorbell_aperture(struct amdgpu_device *adev, in nv_enable_doorbell_aperture() argument
541 adev->nbio.funcs->enable_doorbell_aperture(adev, enable); in nv_enable_doorbell_aperture()
542 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, enable); in nv_enable_doorbell_aperture()
554 void nv_set_virt_ops(struct amdgpu_device *adev) in nv_set_virt_ops() argument
556 adev->virt.ops = &xgpu_nv_virt_ops; in nv_set_virt_ops()
559 static uint32_t nv_get_rev_id(struct amdgpu_device *adev) in nv_get_rev_id() argument
561 return adev->nbio.funcs->get_rev_id(adev); in nv_get_rev_id()
564 static bool nv_need_full_reset(struct amdgpu_device *adev) in nv_need_full_reset() argument
569 static bool nv_need_reset_on_init(struct amdgpu_device *adev) in nv_need_reset_on_init() argument
573 if (adev->flags & AMD_IS_APU) in nv_need_reset_on_init()
586 static uint64_t nv_get_pcie_replay_count(struct amdgpu_device *adev) in nv_get_pcie_replay_count() argument
596 static void nv_init_doorbell_index(struct amdgpu_device *adev) in nv_init_doorbell_index() argument
598 adev->doorbell_index.kiq = AMDGPU_NAVI10_DOORBELL_KIQ; in nv_init_doorbell_index()
599 adev->doorbell_index.mec_ring0 = AMDGPU_NAVI10_DOORBELL_MEC_RING0; in nv_init_doorbell_index()
600 adev->doorbell_index.mec_ring1 = AMDGPU_NAVI10_DOORBELL_MEC_RING1; in nv_init_doorbell_index()
601 adev->doorbell_index.mec_ring2 = AMDGPU_NAVI10_DOORBELL_MEC_RING2; in nv_init_doorbell_index()
602 adev->doorbell_index.mec_ring3 = AMDGPU_NAVI10_DOORBELL_MEC_RING3; in nv_init_doorbell_index()
603 adev->doorbell_index.mec_ring4 = AMDGPU_NAVI10_DOORBELL_MEC_RING4; in nv_init_doorbell_index()
604 adev->doorbell_index.mec_ring5 = AMDGPU_NAVI10_DOORBELL_MEC_RING5; in nv_init_doorbell_index()
605 adev->doorbell_index.mec_ring6 = AMDGPU_NAVI10_DOORBELL_MEC_RING6; in nv_init_doorbell_index()
606 adev->doorbell_index.mec_ring7 = AMDGPU_NAVI10_DOORBELL_MEC_RING7; in nv_init_doorbell_index()
607 adev->doorbell_index.userqueue_start = AMDGPU_NAVI10_DOORBELL_USERQUEUE_START; in nv_init_doorbell_index()
608 adev->doorbell_index.userqueue_end = AMDGPU_NAVI10_DOORBELL_USERQUEUE_END; in nv_init_doorbell_index()
609 adev->doorbell_index.gfx_ring0 = AMDGPU_NAVI10_DOORBELL_GFX_RING0; in nv_init_doorbell_index()
610 adev->doorbell_index.gfx_ring1 = AMDGPU_NAVI10_DOORBELL_GFX_RING1; in nv_init_doorbell_index()
611 adev->doorbell_index.gfx_userqueue_start = in nv_init_doorbell_index()
613 adev->doorbell_index.gfx_userqueue_end = in nv_init_doorbell_index()
615 adev->doorbell_index.mes_ring0 = AMDGPU_NAVI10_DOORBELL_MES_RING0; in nv_init_doorbell_index()
616 adev->doorbell_index.mes_ring1 = AMDGPU_NAVI10_DOORBELL_MES_RING1; in nv_init_doorbell_index()
617 adev->doorbell_index.sdma_engine[0] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0; in nv_init_doorbell_index()
618 adev->doorbell_index.sdma_engine[1] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1; in nv_init_doorbell_index()
619 adev->doorbell_index.sdma_engine[2] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE2; in nv_init_doorbell_index()
620 adev->doorbell_index.sdma_engine[3] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE3; in nv_init_doorbell_index()
621 adev->doorbell_index.ih = AMDGPU_NAVI10_DOORBELL_IH; in nv_init_doorbell_index()
622 adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_NAVI10_DOORBELL64_VCN0_1; in nv_init_doorbell_index()
623 adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_NAVI10_DOORBELL64_VCN2_3; in nv_init_doorbell_index()
624 adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_NAVI10_DOORBELL64_VCN4_5; in nv_init_doorbell_index()
625 adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_NAVI10_DOORBELL64_VCN6_7; in nv_init_doorbell_index()
626 adev->doorbell_index.first_non_cp = AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP; in nv_init_doorbell_index()
627 adev->doorbell_index.last_non_cp = AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP; in nv_init_doorbell_index()
629 adev->doorbell_index.max_assignment = AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT << 1; in nv_init_doorbell_index()
630 adev->doorbell_index.sdma_doorbell_range = 20; in nv_init_doorbell_index()
633 static void nv_pre_asic_init(struct amdgpu_device *adev) in nv_pre_asic_init() argument
637 static int nv_update_umd_stable_pstate(struct amdgpu_device *adev, in nv_update_umd_stable_pstate() argument
641 amdgpu_gfx_rlc_enter_safe_mode(adev); in nv_update_umd_stable_pstate()
643 amdgpu_gfx_rlc_exit_safe_mode(adev); in nv_update_umd_stable_pstate()
645 if (adev->gfx.funcs->update_perfmon_mgcg) in nv_update_umd_stable_pstate()
646 adev->gfx.funcs->update_perfmon_mgcg(adev, !enter); in nv_update_umd_stable_pstate()
648 if (!(adev->flags & AMD_IS_APU) && in nv_update_umd_stable_pstate()
649 (adev->nbio.funcs->enable_aspm) && in nv_update_umd_stable_pstate()
650 amdgpu_device_should_use_aspm(adev)) in nv_update_umd_stable_pstate()
651 adev->nbio.funcs->enable_aspm(adev, !enter); in nv_update_umd_stable_pstate()
681 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in nv_common_early_init() local
683 if (!amdgpu_sriov_vf(adev)) { in nv_common_early_init()
684 adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET; in nv_common_early_init()
685 adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET; in nv_common_early_init()
687 adev->smc_rreg = NULL; in nv_common_early_init()
688 adev->smc_wreg = NULL; in nv_common_early_init()
689 adev->pcie_rreg = &nv_pcie_rreg; in nv_common_early_init()
690 adev->pcie_wreg = &nv_pcie_wreg; in nv_common_early_init()
691 adev->pcie_rreg64 = &nv_pcie_rreg64; in nv_common_early_init()
692 adev->pcie_wreg64 = &nv_pcie_wreg64; in nv_common_early_init()
693 adev->pciep_rreg = amdgpu_device_pcie_port_rreg; in nv_common_early_init()
694 adev->pciep_wreg = amdgpu_device_pcie_port_wreg; in nv_common_early_init()
697 adev->uvd_ctx_rreg = NULL; in nv_common_early_init()
698 adev->uvd_ctx_wreg = NULL; in nv_common_early_init()
700 adev->didt_rreg = &nv_didt_rreg; in nv_common_early_init()
701 adev->didt_wreg = &nv_didt_wreg; in nv_common_early_init()
703 adev->asic_funcs = &nv_asic_funcs; in nv_common_early_init()
705 adev->rev_id = nv_get_rev_id(adev); in nv_common_early_init()
706 adev->external_rev_id = 0xff; in nv_common_early_init()
710 switch (adev->ip_versions[GC_HWIP][0]) { in nv_common_early_init()
712 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in nv_common_early_init()
727 adev->pg_flags = AMD_PG_SUPPORT_VCN | in nv_common_early_init()
731 adev->external_rev_id = adev->rev_id + 0x1; in nv_common_early_init()
734 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in nv_common_early_init()
749 adev->pg_flags = AMD_PG_SUPPORT_VCN | in nv_common_early_init()
752 adev->external_rev_id = adev->rev_id + 20; in nv_common_early_init()
755 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in nv_common_early_init()
771 adev->pg_flags = AMD_PG_SUPPORT_VCN | in nv_common_early_init()
779 if (amdgpu_sriov_vf(adev)) in nv_common_early_init()
780 adev->rev_id = 0; in nv_common_early_init()
781 adev->external_rev_id = adev->rev_id + 0xa; in nv_common_early_init()
784 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in nv_common_early_init()
795 adev->pg_flags = AMD_PG_SUPPORT_VCN | in nv_common_early_init()
800 if (amdgpu_sriov_vf(adev)) { in nv_common_early_init()
802 adev->cg_flags = 0; in nv_common_early_init()
803 adev->pg_flags = 0; in nv_common_early_init()
805 adev->external_rev_id = adev->rev_id + 0x28; in nv_common_early_init()
808 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in nv_common_early_init()
819 adev->pg_flags = AMD_PG_SUPPORT_VCN | in nv_common_early_init()
824 adev->external_rev_id = adev->rev_id + 0x32; in nv_common_early_init()
827 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in nv_common_early_init()
842 adev->pg_flags = AMD_PG_SUPPORT_GFX_PG | in nv_common_early_init()
846 if (adev->apu_flags & AMD_APU_IS_VANGOGH) in nv_common_early_init()
847 adev->external_rev_id = adev->rev_id + 0x01; in nv_common_early_init()
850 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in nv_common_early_init()
861 adev->pg_flags = AMD_PG_SUPPORT_VCN | in nv_common_early_init()
866 adev->external_rev_id = adev->rev_id + 0x3c; in nv_common_early_init()
869 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in nv_common_early_init()
879 adev->pg_flags = AMD_PG_SUPPORT_VCN | in nv_common_early_init()
883 adev->external_rev_id = adev->rev_id + 0x46; in nv_common_early_init()
886 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in nv_common_early_init()
905 adev->pg_flags = AMD_PG_SUPPORT_GFX_PG | in nv_common_early_init()
909 if (adev->pdev->device == 0x1681) in nv_common_early_init()
910 adev->external_rev_id = 0x20; in nv_common_early_init()
912 adev->external_rev_id = adev->rev_id + 0x01; in nv_common_early_init()
916 adev->cg_flags = 0; in nv_common_early_init()
917 adev->pg_flags = 0; in nv_common_early_init()
918 adev->external_rev_id = adev->rev_id + 0x82; in nv_common_early_init()
921 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in nv_common_early_init()
940 adev->pg_flags = AMD_PG_SUPPORT_GFX_PG | in nv_common_early_init()
944 adev->external_rev_id = adev->rev_id + 0x01; in nv_common_early_init()
947 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in nv_common_early_init()
966 adev->pg_flags = AMD_PG_SUPPORT_VCN | in nv_common_early_init()
970 adev->external_rev_id = adev->rev_id + 0x01; in nv_common_early_init()
977 if (adev->harvest_ip_mask & AMD_HARVEST_IP_VCN_MASK) in nv_common_early_init()
978 adev->pg_flags &= ~(AMD_PG_SUPPORT_VCN | in nv_common_early_init()
982 if (amdgpu_sriov_vf(adev)) { in nv_common_early_init()
983 amdgpu_virt_init_setting(adev); in nv_common_early_init()
984 xgpu_nv_mailbox_set_irq_funcs(adev); in nv_common_early_init()
992 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in nv_common_late_init() local
994 if (amdgpu_sriov_vf(adev)) { in nv_common_late_init()
995 xgpu_nv_mailbox_get_irq(adev); in nv_common_late_init()
996 amdgpu_virt_update_sriov_video_codec(adev, in nv_common_late_init()
1006 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in nv_common_sw_init() local
1008 if (amdgpu_sriov_vf(adev)) in nv_common_sw_init()
1009 xgpu_nv_mailbox_add_irq_id(adev); in nv_common_sw_init()
1021 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in nv_common_hw_init() local
1023 if (adev->nbio.funcs->apply_lc_spc_mode_wa) in nv_common_hw_init()
1024 adev->nbio.funcs->apply_lc_spc_mode_wa(adev); in nv_common_hw_init()
1026 if (adev->nbio.funcs->apply_l1_link_width_reconfig_wa) in nv_common_hw_init()
1027 adev->nbio.funcs->apply_l1_link_width_reconfig_wa(adev); in nv_common_hw_init()
1030 nv_pcie_gen3_enable(adev); in nv_common_hw_init()
1032 nv_program_aspm(adev); in nv_common_hw_init()
1034 adev->nbio.funcs->init_registers(adev); in nv_common_hw_init()
1039 if (adev->nbio.funcs->remap_hdp_registers && !amdgpu_sriov_vf(adev)) in nv_common_hw_init()
1040 adev->nbio.funcs->remap_hdp_registers(adev); in nv_common_hw_init()
1042 nv_enable_doorbell_aperture(adev, true); in nv_common_hw_init()
1049 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in nv_common_hw_fini() local
1052 nv_enable_doorbell_aperture(adev, false); in nv_common_hw_fini()
1059 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in nv_common_suspend() local
1061 return nv_common_hw_fini(adev); in nv_common_suspend()
1066 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in nv_common_resume() local
1068 return nv_common_hw_init(adev); in nv_common_resume()
1089 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in nv_common_set_clockgating_state() local
1091 if (amdgpu_sriov_vf(adev)) in nv_common_set_clockgating_state()
1094 switch (adev->ip_versions[NBIO_HWIP][0]) { in nv_common_set_clockgating_state()
1102 adev->nbio.funcs->update_medium_grain_clock_gating(adev, in nv_common_set_clockgating_state()
1104 adev->nbio.funcs->update_medium_grain_light_sleep(adev, in nv_common_set_clockgating_state()
1106 adev->hdp.funcs->update_clock_gating(adev, in nv_common_set_clockgating_state()
1108 adev->smuio.funcs->update_rom_clock_gating(adev, in nv_common_set_clockgating_state()
1126 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in nv_common_get_clockgating_state() local
1128 if (amdgpu_sriov_vf(adev)) in nv_common_get_clockgating_state()
1131 adev->nbio.funcs->get_clockgating_state(adev, flags); in nv_common_get_clockgating_state()
1133 adev->hdp.funcs->get_clock_gating_state(adev, flags); in nv_common_get_clockgating_state()
1135 adev->smuio.funcs->get_clock_gating_state(adev, flags); in nv_common_get_clockgating_state()