181 			adev->virt.fw_reserve.checksum_key =  in xgpu_ai_send_access_requests()
189 		adev->virt.req_init_data_ver = 0;	  in xgpu_ai_send_access_requests()
254 	struct amdgpu_virt *virt = container_of(work, struct amdgpu_virt, flr_work);  in xgpu_ai_mailbox_flr_work()  local
255 	struct amdgpu_device *adev = container_of(virt, struct amdgpu_device, virt);  in xgpu_ai_mailbox_flr_work()
322 								&adev->virt.flr_work),  in xgpu_ai_mailbox_rcv_irq()
355 	adev->virt.ack_irq.num_types = 1;  in xgpu_ai_mailbox_set_irq_funcs()
356 	adev->virt.ack_irq.funcs = &xgpu_ai_mailbox_ack_irq_funcs;  in xgpu_ai_mailbox_set_irq_funcs()
357 	adev->virt.rcv_irq.num_types = 1;  in xgpu_ai_mailbox_set_irq_funcs()
358 	adev->virt.rcv_irq.funcs = &xgpu_ai_mailbox_rcv_irq_funcs;  in xgpu_ai_mailbox_set_irq_funcs()
365 	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_BIF, 135, &adev->virt.rcv_irq);  in xgpu_ai_mailbox_add_irq_id()
369 	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_BIF, 138, &adev->virt.ack_irq);  in xgpu_ai_mailbox_add_irq_id()
371 		amdgpu_irq_put(adev, &adev->virt.rcv_irq, 0);  in xgpu_ai_mailbox_add_irq_id()
382 	r = amdgpu_irq_get(adev, &adev->virt.rcv_irq, 0);  in xgpu_ai_mailbox_get_irq()
385 	r = amdgpu_irq_get(adev, &adev->virt.ack_irq, 0);  in xgpu_ai_mailbox_get_irq()
387 		amdgpu_irq_put(adev, &adev->virt.rcv_irq, 0);  in xgpu_ai_mailbox_get_irq()
391 	INIT_WORK(&adev->virt.flr_work, xgpu_ai_mailbox_flr_work);  in xgpu_ai_mailbox_get_irq()
398 	amdgpu_irq_put(adev, &adev->virt.ack_irq, 0);  in xgpu_ai_mailbox_put_irq()
399 	amdgpu_irq_put(adev, &adev->virt.rcv_irq, 0);  in xgpu_ai_mailbox_put_irq()