714 	struct v10_compute_mqd *mqd = ring->mqd_ptr;  in mes_v10_1_mqd_init()  local
718 	mqd->header = 0xC0310800;  in mes_v10_1_mqd_init()
719 	mqd->compute_pipelinestat_enable = 0x00000001;  in mes_v10_1_mqd_init()
720 	mqd->compute_static_thread_mgmt_se0 = 0xffffffff;  in mes_v10_1_mqd_init()
721 	mqd->compute_static_thread_mgmt_se1 = 0xffffffff;  in mes_v10_1_mqd_init()
722 	mqd->compute_static_thread_mgmt_se2 = 0xffffffff;  in mes_v10_1_mqd_init()
723 	mqd->compute_static_thread_mgmt_se3 = 0xffffffff;  in mes_v10_1_mqd_init()
724 	mqd->compute_misc_reserved = 0x00000003;  in mes_v10_1_mqd_init()
733 	mqd->cp_hqd_eop_base_addr_lo = lower_32_bits(eop_base_addr);  in mes_v10_1_mqd_init()
734 	mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);  in mes_v10_1_mqd_init()
735 	mqd->cp_hqd_eop_control = tmp;  in mes_v10_1_mqd_init()
739 	mqd->cp_hqd_pq_rptr = 0;  in mes_v10_1_mqd_init()
740 	mqd->cp_hqd_pq_wptr_lo = 0;  in mes_v10_1_mqd_init()
741 	mqd->cp_hqd_pq_wptr_hi = 0;  in mes_v10_1_mqd_init()
744 	mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc;  in mes_v10_1_mqd_init()
745 	mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);  in mes_v10_1_mqd_init()
750 	mqd->cp_mqd_control = tmp;  in mes_v10_1_mqd_init()
754 	mqd->cp_hqd_pq_base_lo = lower_32_bits(hqd_gpu_addr);  in mes_v10_1_mqd_init()
755 	mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);  in mes_v10_1_mqd_init()
759 	mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;  in mes_v10_1_mqd_init()
760 	mqd->cp_hqd_pq_rptr_report_addr_hi =  in mes_v10_1_mqd_init()
765 	mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffff8;  in mes_v10_1_mqd_init()
766 	mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;  in mes_v10_1_mqd_init()
782 	mqd->cp_hqd_pq_control = tmp;  in mes_v10_1_mqd_init()
799 	mqd->cp_hqd_pq_doorbell_control = tmp;  in mes_v10_1_mqd_init()
801 	mqd->cp_hqd_vmid = 0;  in mes_v10_1_mqd_init()
803 	mqd->cp_hqd_active = 1;  in mes_v10_1_mqd_init()
804 	mqd->cp_hqd_persistent_state = mmCP_HQD_PERSISTENT_STATE_DEFAULT;  in mes_v10_1_mqd_init()
805 	mqd->cp_hqd_ib_control = mmCP_HQD_IB_CONTROL_DEFAULT;  in mes_v10_1_mqd_init()
806 	mqd->cp_hqd_iq_timer = mmCP_HQD_IQ_TIMER_DEFAULT;  in mes_v10_1_mqd_init()
807 	mqd->cp_hqd_quantum = mmCP_HQD_QUANTUM_DEFAULT;  in mes_v10_1_mqd_init()
812 	mqd->cp_hqd_suspend_cntl_stack_offset = tmp;  in mes_v10_1_mqd_init()
820 	struct v10_compute_mqd *mqd = ring->mqd_ptr;
839 	WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr_lo);
840 	WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi);
848 	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE, mqd->cp_hqd_pq_base_lo);
849 	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI, mqd->cp_hqd_pq_base_hi);
853 		     mqd->cp_hqd_pq_rptr_report_addr_lo);
855 		     mqd->cp_hqd_pq_rptr_report_addr_hi);
858 	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL, mqd->cp_hqd_pq_control);
862 		     mqd->cp_hqd_pq_wptr_poll_addr_lo);
864 		     mqd->cp_hqd_pq_wptr_poll_addr_hi);
868 		     mqd->cp_hqd_pq_doorbell_control);
871 	WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE, mqd->cp_hqd_persistent_state);
874 	WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, mqd->cp_hqd_active);