Lines Matching refs:mes
89 static int mes_v10_1_submit_pkt_and_poll_completion(struct amdgpu_mes *mes, in mes_v10_1_submit_pkt_and_poll_completion() argument
97 struct amdgpu_device *adev = mes->adev; in mes_v10_1_submit_pkt_and_poll_completion()
98 struct amdgpu_ring *ring = &mes->ring; in mes_v10_1_submit_pkt_and_poll_completion()
103 spin_lock_irqsave(&mes->ring_lock, flags); in mes_v10_1_submit_pkt_and_poll_completion()
105 spin_unlock_irqrestore(&mes->ring_lock, flags); in mes_v10_1_submit_pkt_and_poll_completion()
110 api_status->api_completion_fence_addr = mes->ring.fence_drv.gpu_addr; in mes_v10_1_submit_pkt_and_poll_completion()
111 api_status->api_completion_fence_value = ++mes->ring.fence_drv.sync_seq; in mes_v10_1_submit_pkt_and_poll_completion()
115 spin_unlock_irqrestore(&mes->ring_lock, flags); in mes_v10_1_submit_pkt_and_poll_completion()
143 static int mes_v10_1_add_hw_queue(struct amdgpu_mes *mes, in mes_v10_1_add_hw_queue() argument
146 struct amdgpu_device *adev = mes->adev; in mes_v10_1_add_hw_queue()
180 return mes_v10_1_submit_pkt_and_poll_completion(mes, in mes_v10_1_add_hw_queue()
185 static int mes_v10_1_remove_hw_queue(struct amdgpu_mes *mes, in mes_v10_1_remove_hw_queue() argument
199 return mes_v10_1_submit_pkt_and_poll_completion(mes, in mes_v10_1_remove_hw_queue()
204 static int mes_v10_1_unmap_legacy_queue(struct amdgpu_mes *mes, in mes_v10_1_unmap_legacy_queue() argument
233 return mes_v10_1_submit_pkt_and_poll_completion(mes, in mes_v10_1_unmap_legacy_queue()
238 static int mes_v10_1_suspend_gang(struct amdgpu_mes *mes, in mes_v10_1_suspend_gang() argument
244 static int mes_v10_1_resume_gang(struct amdgpu_mes *mes, in mes_v10_1_resume_gang() argument
250 static int mes_v10_1_query_sched_status(struct amdgpu_mes *mes) in mes_v10_1_query_sched_status() argument
260 return mes_v10_1_submit_pkt_and_poll_completion(mes, in mes_v10_1_query_sched_status()
265 static int mes_v10_1_set_hw_resources(struct amdgpu_mes *mes) in mes_v10_1_set_hw_resources() argument
268 struct amdgpu_device *adev = mes->adev; in mes_v10_1_set_hw_resources()
277 mes_set_hw_res_pkt.vmid_mask_mmhub = mes->vmid_mask_mmhub; in mes_v10_1_set_hw_resources()
278 mes_set_hw_res_pkt.vmid_mask_gfxhub = mes->vmid_mask_gfxhub; in mes_v10_1_set_hw_resources()
281 mes_set_hw_res_pkt.g_sch_ctx_gpu_mc_ptr = mes->sch_ctx_gpu_addr; in mes_v10_1_set_hw_resources()
283 mes->query_status_fence_gpu_addr; in mes_v10_1_set_hw_resources()
287 mes->compute_hqd_mask[i]; in mes_v10_1_set_hw_resources()
290 mes_set_hw_res_pkt.gfx_hqd_mask[i] = mes->gfx_hqd_mask[i]; in mes_v10_1_set_hw_resources()
293 mes_set_hw_res_pkt.sdma_hqd_mask[i] = mes->sdma_hqd_mask[i]; in mes_v10_1_set_hw_resources()
297 mes->aggregated_doorbells[i]; in mes_v10_1_set_hw_resources()
311 return mes_v10_1_submit_pkt_and_poll_completion(mes, in mes_v10_1_set_hw_resources()
316 static void mes_v10_1_init_aggregated_doorbell(struct amdgpu_mes *mes) in mes_v10_1_init_aggregated_doorbell() argument
318 struct amdgpu_device *adev = mes->adev; in mes_v10_1_init_aggregated_doorbell()
325 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_LOW] << in mes_v10_1_init_aggregated_doorbell()
334 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_NORMAL] << in mes_v10_1_init_aggregated_doorbell()
343 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_MEDIUM] << in mes_v10_1_init_aggregated_doorbell()
352 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_HIGH] << in mes_v10_1_init_aggregated_doorbell()
361 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_REALTIME] << in mes_v10_1_init_aggregated_doorbell()
405 err = request_firmware(&adev->mes.fw[pipe], fw_name, adev->dev); in mes_v10_1_init_microcode()
409 err = amdgpu_ucode_validate(adev->mes.fw[pipe]); in mes_v10_1_init_microcode()
411 release_firmware(adev->mes.fw[pipe]); in mes_v10_1_init_microcode()
412 adev->mes.fw[pipe] = NULL; in mes_v10_1_init_microcode()
417 adev->mes.fw[pipe]->data; in mes_v10_1_init_microcode()
418 adev->mes.ucode_fw_version[pipe] = in mes_v10_1_init_microcode()
420 adev->mes.ucode_fw_version[pipe] = in mes_v10_1_init_microcode()
422 adev->mes.uc_start_addr[pipe] = in mes_v10_1_init_microcode()
425 adev->mes.data_start_addr[pipe] = in mes_v10_1_init_microcode()
442 info->fw = adev->mes.fw[pipe]; in mes_v10_1_init_microcode()
449 info->fw = adev->mes.fw[pipe]; in mes_v10_1_init_microcode()
461 release_firmware(adev->mes.fw[pipe]); in mes_v10_1_free_microcode()
462 adev->mes.fw[pipe] = NULL; in mes_v10_1_free_microcode()
474 adev->mes.fw[pipe]->data; in mes_v10_1_allocate_ucode_buffer()
476 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + in mes_v10_1_allocate_ucode_buffer()
482 &adev->mes.ucode_fw_obj[pipe], in mes_v10_1_allocate_ucode_buffer()
483 &adev->mes.ucode_fw_gpu_addr[pipe], in mes_v10_1_allocate_ucode_buffer()
484 (void **)&adev->mes.ucode_fw_ptr[pipe]); in mes_v10_1_allocate_ucode_buffer()
490 memcpy(adev->mes.ucode_fw_ptr[pipe], fw_data, fw_size); in mes_v10_1_allocate_ucode_buffer()
492 amdgpu_bo_kunmap(adev->mes.ucode_fw_obj[pipe]); in mes_v10_1_allocate_ucode_buffer()
493 amdgpu_bo_unreserve(adev->mes.ucode_fw_obj[pipe]); in mes_v10_1_allocate_ucode_buffer()
507 adev->mes.fw[pipe]->data; in mes_v10_1_allocate_ucode_data_buffer()
509 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + in mes_v10_1_allocate_ucode_data_buffer()
515 &adev->mes.data_fw_obj[pipe], in mes_v10_1_allocate_ucode_data_buffer()
516 &adev->mes.data_fw_gpu_addr[pipe], in mes_v10_1_allocate_ucode_data_buffer()
517 (void **)&adev->mes.data_fw_ptr[pipe]); in mes_v10_1_allocate_ucode_data_buffer()
523 memcpy(adev->mes.data_fw_ptr[pipe], fw_data, fw_size); in mes_v10_1_allocate_ucode_data_buffer()
525 amdgpu_bo_kunmap(adev->mes.data_fw_obj[pipe]); in mes_v10_1_allocate_ucode_data_buffer()
526 amdgpu_bo_unreserve(adev->mes.data_fw_obj[pipe]); in mes_v10_1_allocate_ucode_data_buffer()
534 amdgpu_bo_free_kernel(&adev->mes.data_fw_obj[pipe], in mes_v10_1_free_ucode_buffers()
535 &adev->mes.data_fw_gpu_addr[pipe], in mes_v10_1_free_ucode_buffers()
536 (void **)&adev->mes.data_fw_ptr[pipe]); in mes_v10_1_free_ucode_buffers()
538 amdgpu_bo_free_kernel(&adev->mes.ucode_fw_obj[pipe], in mes_v10_1_free_ucode_buffers()
539 &adev->mes.ucode_fw_gpu_addr[pipe], in mes_v10_1_free_ucode_buffers()
540 (void **)&adev->mes.ucode_fw_ptr[pipe]); in mes_v10_1_free_ucode_buffers()
562 (uint32_t)(adev->mes.uc_start_addr[pipe]) >> 2); in mes_v10_1_enable()
602 if (!adev->mes.fw[pipe]) in mes_v10_1_load_microcode()
623 (uint32_t)(adev->mes.uc_start_addr[pipe]) >> 2); in mes_v10_1_load_microcode()
627 lower_32_bits(adev->mes.ucode_fw_gpu_addr[pipe])); in mes_v10_1_load_microcode()
629 upper_32_bits(adev->mes.ucode_fw_gpu_addr[pipe])); in mes_v10_1_load_microcode()
636 lower_32_bits(adev->mes.data_fw_gpu_addr[pipe])); in mes_v10_1_load_microcode()
638 upper_32_bits(adev->mes.data_fw_gpu_addr[pipe])); in mes_v10_1_load_microcode()
696 &adev->mes.eop_gpu_obj[pipe], in mes_v10_1_allocate_eop_buf()
697 &adev->mes.eop_gpu_addr[pipe], in mes_v10_1_allocate_eop_buf()
704 memset(eop, 0, adev->mes.eop_gpu_obj[pipe]->tbo.base.size); in mes_v10_1_allocate_eop_buf()
706 amdgpu_bo_kunmap(adev->mes.eop_gpu_obj[pipe]); in mes_v10_1_allocate_eop_buf()
707 amdgpu_bo_unreserve(adev->mes.eop_gpu_obj[pipe]); in mes_v10_1_allocate_eop_buf()
896 kiq->pmf->kiq_map_queues(kiq_ring, &adev->mes.ring); in mes_v10_1_kiq_enable_queue()
911 r = mes_v10_1_mqd_init(&adev->mes.ring); in mes_v10_1_queue_init()
926 ring = &adev->mes.ring; in mes_v10_1_ring_init()
937 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_SCHED_PIPE]; in mes_v10_1_ring_init()
961 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_KIQ_PIPE]; in mes_v10_1_kiq_ring_init()
979 ring = &adev->mes.ring; in mes_v10_1_mqd_sw_init()
996 adev->mes.mqd_backup[pipe] = kmalloc(mqd_size, GFP_KERNEL); in mes_v10_1_mqd_sw_init()
997 if (!adev->mes.mqd_backup[pipe]) in mes_v10_1_mqd_sw_init()
1010 adev->mes.adev = adev; in mes_v10_1_sw_init()
1011 adev->mes.funcs = &mes_v10_1_funcs; in mes_v10_1_sw_init()
1012 adev->mes.kiq_hw_init = &mes_v10_1_kiq_hw_init; in mes_v10_1_sw_init()
1053 amdgpu_device_wb_free(adev, adev->mes.sch_ctx_offs); in mes_v10_1_sw_fini()
1054 amdgpu_device_wb_free(adev, adev->mes.query_status_fence_offs); in mes_v10_1_sw_fini()
1057 kfree(adev->mes.mqd_backup[pipe]); in mes_v10_1_sw_fini()
1059 amdgpu_bo_free_kernel(&adev->mes.eop_gpu_obj[pipe], in mes_v10_1_sw_fini()
1060 &adev->mes.eop_gpu_addr[pipe], in mes_v10_1_sw_fini()
1070 amdgpu_bo_free_kernel(&adev->mes.ring.mqd_obj, in mes_v10_1_sw_fini()
1071 &adev->mes.ring.mqd_gpu_addr, in mes_v10_1_sw_fini()
1072 &adev->mes.ring.mqd_ptr); in mes_v10_1_sw_fini()
1075 amdgpu_ring_fini(&adev->mes.ring); in mes_v10_1_sw_fini()
1165 r = mes_v10_1_set_hw_resources(&adev->mes); in mes_v10_1_hw_init()
1169 mes_v10_1_init_aggregated_doorbell(&adev->mes); in mes_v10_1_hw_init()
1171 r = mes_v10_1_query_sched_status(&adev->mes); in mes_v10_1_hw_init()
1183 adev->mes.ring.sched.ready = true; in mes_v10_1_hw_init()
1196 adev->mes.ring.sched.ready = false; in mes_v10_1_hw_fini()