54 	adev->jpeg.num_jpeg_inst = 1;  in jpeg_v4_0_early_init()
77 		VCN_4_0__SRCID__JPEG_DECODE, &adev->jpeg.inst->irq);  in jpeg_v4_0_sw_init()
89 	ring = &adev->jpeg.inst->ring_dec;  in jpeg_v4_0_sw_init()
93 	r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq, 0,  in jpeg_v4_0_sw_init()
98 	adev->jpeg.internal.jpeg_pitch = regUVD_JPEG_PITCH_INTERNAL_OFFSET;  in jpeg_v4_0_sw_init()
99 	adev->jpeg.inst->external.jpeg_pitch = SOC15_REG_OFFSET(JPEG, 0, regUVD_JPEG_PITCH);  in jpeg_v4_0_sw_init()
134 	struct amdgpu_ring *ring = &adev->jpeg.inst->ring_dec;  in jpeg_v4_0_hw_init()
166 	if (adev->jpeg.cur_state != AMD_PG_STATE_GATE &&  in jpeg_v4_0_hw_fini()
329 	struct amdgpu_ring *ring = &adev->jpeg.inst->ring_dec;  in jpeg_v4_0_start()
495 	if (state == adev->jpeg.cur_state)  in jpeg_v4_0_set_powergating_state()
504 		adev->jpeg.cur_state = state;  in jpeg_v4_0_set_powergating_state()
525 		amdgpu_fence_process(&adev->jpeg.inst->ring_dec);  in jpeg_v4_0_process_interrupt()
588 	adev->jpeg.inst->ring_dec.funcs = &jpeg_v4_0_dec_ring_vm_funcs;  in jpeg_v4_0_set_dec_ring_funcs()
599 	adev->jpeg.inst->irq.num_types = 1;  in jpeg_v4_0_set_irq_funcs()
600 	adev->jpeg.inst->irq.funcs = &jpeg_v4_0_irq_funcs;  in jpeg_v4_0_set_irq_funcs()