54 	adev->jpeg.num_jpeg_inst = 1;  in jpeg_v4_0_early_init()
63  * jpeg_v4_0_sw_init - sw init for JPEG block
75 	/* JPEG TRAP */  in jpeg_v4_0_sw_init()
77 		VCN_4_0__SRCID__JPEG_DECODE, &adev->jpeg.inst->irq);  in jpeg_v4_0_sw_init()
89 	ring = &adev->jpeg.inst->ring_dec;  in jpeg_v4_0_sw_init()
93 	r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq, 0,  in jpeg_v4_0_sw_init()
98 	adev->jpeg.internal.jpeg_pitch = regUVD_JPEG_PITCH_INTERNAL_OFFSET;  in jpeg_v4_0_sw_init()
99 	adev->jpeg.inst->external.jpeg_pitch = SOC15_REG_OFFSET(JPEG, 0, regUVD_JPEG_PITCH);  in jpeg_v4_0_sw_init()
105  * jpeg_v4_0_sw_fini - sw fini for JPEG block
109  * JPEG suspend and free up sw allocation
126  * jpeg_v4_0_hw_init - start and test JPEG block
134 	struct amdgpu_ring *ring = &adev->jpeg.inst->ring_dec;  in jpeg_v4_0_hw_init()
148 	DRM_DEV_INFO(adev->dev, "JPEG decode initialized successfully.\n");  in jpeg_v4_0_hw_init()
158  * Stop the JPEG block, mark ring as not ready any more
166 	if (adev->jpeg.cur_state != AMD_PG_STATE_GATE &&  in jpeg_v4_0_hw_fini()
167 	      RREG32_SOC15(JPEG, 0, regUVD_JRBC_STATUS))  in jpeg_v4_0_hw_fini()
174  * jpeg_v4_0_suspend - suspend JPEG block
178  * HW fini and suspend JPEG block
195  * jpeg_v4_0_resume - resume JPEG block
199  * Resume firmware and hw init JPEG block
219 	data = RREG32_SOC15(JPEG, 0, regJPEG_CGC_CTRL);  in jpeg_v4_0_disable_clock_gating()
229 	WREG32_SOC15(JPEG, 0, regJPEG_CGC_CTRL, data);  in jpeg_v4_0_disable_clock_gating()
231 	data = RREG32_SOC15(JPEG, 0, regJPEG_CGC_GATE);  in jpeg_v4_0_disable_clock_gating()
236 	WREG32_SOC15(JPEG, 0, regJPEG_CGC_GATE, data);  in jpeg_v4_0_disable_clock_gating()
243 	data = RREG32_SOC15(JPEG, 0, regJPEG_CGC_CTRL);  in jpeg_v4_0_enable_clock_gating()
253 	WREG32_SOC15(JPEG, 0, regJPEG_CGC_CTRL, data);  in jpeg_v4_0_enable_clock_gating()
255 	data = RREG32_SOC15(JPEG, 0, regJPEG_CGC_GATE);  in jpeg_v4_0_enable_clock_gating()
260 	WREG32_SOC15(JPEG, 0, regJPEG_CGC_GATE, data);  in jpeg_v4_0_enable_clock_gating()
270 		WREG32(SOC15_REG_OFFSET(JPEG, 0, regUVD_PGFSM_CONFIG), data);  in jpeg_v4_0_disable_static_power_gating()
272 		r = SOC15_WAIT_ON_RREG(JPEG, 0,  in jpeg_v4_0_disable_static_power_gating()
277 			DRM_DEV_ERROR(adev->dev, "amdgpu: JPEG disable power gating failed\n");  in jpeg_v4_0_disable_static_power_gating()
283 	WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JPEG_POWER_STATUS), 0,  in jpeg_v4_0_disable_static_power_gating()
286 	/* keep the JPEG in static PG mode */  in jpeg_v4_0_disable_static_power_gating()
287 	WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JPEG_POWER_STATUS), 0,  in jpeg_v4_0_disable_static_power_gating()
296 	WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JPEG_POWER_STATUS),  in jpeg_v4_0_enable_static_power_gating()
305 		WREG32(SOC15_REG_OFFSET(JPEG, 0, regUVD_PGFSM_CONFIG), data);  in jpeg_v4_0_enable_static_power_gating()
307 		r = SOC15_WAIT_ON_RREG(JPEG, 0, regUVD_PGFSM_STATUS,  in jpeg_v4_0_enable_static_power_gating()
312 			DRM_DEV_ERROR(adev->dev, "amdgpu: JPEG enable power gating failed\n");  in jpeg_v4_0_enable_static_power_gating()
321  * jpeg_v4_0_start - start JPEG block
325  * Setup and start the JPEG block
329 	struct amdgpu_ring *ring = &adev->jpeg.inst->ring_dec;  in jpeg_v4_0_start()
340 	/* JPEG disable CGC */  in jpeg_v4_0_start()
344 	WREG32_SOC15(JPEG, 0, regJPEG_DEC_GFX10_ADDR_CONFIG,  in jpeg_v4_0_start()
349 	WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JMI_CNTL), 0,  in jpeg_v4_0_start()
353 	WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regJPEG_SYS_INT_EN),  in jpeg_v4_0_start()
357 	WREG32_SOC15(JPEG, 0, regUVD_LMI_JRBC_RB_VMID, 0);  in jpeg_v4_0_start()
358 	WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_CNTL, (0x00000001L | 0x00000002L));  in jpeg_v4_0_start()
359 	WREG32_SOC15(JPEG, 0, regUVD_LMI_JRBC_RB_64BIT_BAR_LOW,  in jpeg_v4_0_start()
361 	WREG32_SOC15(JPEG, 0, regUVD_LMI_JRBC_RB_64BIT_BAR_HIGH,  in jpeg_v4_0_start()
363 	WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_RPTR, 0);  in jpeg_v4_0_start()
364 	WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_WPTR, 0);  in jpeg_v4_0_start()
365 	WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_CNTL, 0x00000002L);  in jpeg_v4_0_start()
366 	WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_SIZE, ring->ring_size / 4);  in jpeg_v4_0_start()
367 	ring->wptr = RREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_WPTR);  in jpeg_v4_0_start()
373  * jpeg_v4_0_stop - stop JPEG block
377  * stop the JPEG block
384 	WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JMI_CNTL),  in jpeg_v4_0_stop()
412 	return RREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_RPTR);  in jpeg_v4_0_dec_ring_get_rptr()
429 		return RREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_WPTR);  in jpeg_v4_0_dec_ring_get_wptr()
447 		WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr));  in jpeg_v4_0_dec_ring_set_wptr()
456 	ret &= (((RREG32_SOC15(JPEG, 0, regUVD_JRBC_STATUS) &  in jpeg_v4_0_is_idle()
467 	return SOC15_WAIT_ON_RREG(JPEG, 0, regUVD_JRBC_STATUS,  in jpeg_v4_0_wait_for_idle()
495 	if (state == adev->jpeg.cur_state)  in jpeg_v4_0_set_powergating_state()
504 		adev->jpeg.cur_state = state;  in jpeg_v4_0_set_powergating_state()
521 	DRM_DEBUG("IH: JPEG TRAP\n");  in jpeg_v4_0_process_interrupt()
525 		amdgpu_fence_process(&adev->jpeg.inst->ring_dec);  in jpeg_v4_0_process_interrupt()
588 	adev->jpeg.inst->ring_dec.funcs = &jpeg_v4_0_dec_ring_vm_funcs;  in jpeg_v4_0_set_dec_ring_funcs()
589 	DRM_DEV_INFO(adev->dev, "JPEG decode is enabled in VM mode\n");  in jpeg_v4_0_set_dec_ring_funcs()
599 	adev->jpeg.inst->irq.num_types = 1;  in jpeg_v4_0_set_irq_funcs()
600 	adev->jpeg.inst->irq.funcs = &jpeg_v4_0_irq_funcs;  in jpeg_v4_0_set_irq_funcs()