65 	adev->jpeg.num_jpeg_inst = 1;  in jpeg_v3_0_early_init()
88 		VCN_2_0__SRCID__JPEG_DECODE, &adev->jpeg.inst->irq);  in jpeg_v3_0_sw_init()
100 	ring = &adev->jpeg.inst->ring_dec;  in jpeg_v3_0_sw_init()
104 	r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq, 0,  in jpeg_v3_0_sw_init()
109 	adev->jpeg.internal.jpeg_pitch = mmUVD_JPEG_PITCH_INTERNAL_OFFSET;  in jpeg_v3_0_sw_init()
110 	adev->jpeg.inst->external.jpeg_pitch = SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_PITCH);  in jpeg_v3_0_sw_init()
145 	struct amdgpu_ring *ring = &adev->jpeg.inst->ring_dec;  in jpeg_v3_0_hw_init()
173 	if (adev->jpeg.cur_state != AMD_PG_STATE_GATE &&  in jpeg_v3_0_hw_fini()
331 	struct amdgpu_ring *ring = &adev->jpeg.inst->ring_dec;  in jpeg_v3_0_start()
498 	if(state == adev->jpeg.cur_state)  in jpeg_v3_0_set_powergating_state()
507 		adev->jpeg.cur_state = state;  in jpeg_v3_0_set_powergating_state()
528 		amdgpu_fence_process(&adev->jpeg.inst->ring_dec);  in jpeg_v3_0_process_interrupt()
591 	adev->jpeg.inst->ring_dec.funcs = &jpeg_v3_0_dec_ring_vm_funcs;  in jpeg_v3_0_set_dec_ring_funcs()
602 	adev->jpeg.inst->irq.num_types = 1;  in jpeg_v3_0_set_irq_funcs()
603 	adev->jpeg.inst->irq.funcs = &jpeg_v3_0_irq_funcs;  in jpeg_v3_0_set_irq_funcs()