Lines Matching full:jpeg
63 adev->jpeg.num_jpeg_inst = JPEG25_MAX_HW_INSTANCES_ARCTURUS; in jpeg_v2_5_early_init()
64 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) { in jpeg_v2_5_early_init()
65 harvest = RREG32_SOC15(JPEG, i, mmCC_UVD_HARVESTING); in jpeg_v2_5_early_init()
67 adev->jpeg.harvest_config |= 1 << i; in jpeg_v2_5_early_init()
69 if (adev->jpeg.harvest_config == (AMDGPU_JPEG_HARVEST_JPEG0 | in jpeg_v2_5_early_init()
81 * jpeg_v2_5_sw_init - sw init for JPEG block
93 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { in jpeg_v2_5_sw_init()
94 if (adev->jpeg.harvest_config & (1 << i)) in jpeg_v2_5_sw_init()
97 /* JPEG TRAP */ in jpeg_v2_5_sw_init()
99 VCN_2_0__SRCID__JPEG_DECODE, &adev->jpeg.inst[i].irq); in jpeg_v2_5_sw_init()
103 /* JPEG DJPEG POISON EVENT */ in jpeg_v2_5_sw_init()
105 VCN_2_6__SRCID_DJPEG0_POISON, &adev->jpeg.inst[i].irq); in jpeg_v2_5_sw_init()
109 /* JPEG EJPEG POISON EVENT */ in jpeg_v2_5_sw_init()
111 VCN_2_6__SRCID_EJPEG0_POISON, &adev->jpeg.inst[i].irq); in jpeg_v2_5_sw_init()
124 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { in jpeg_v2_5_sw_init()
125 if (adev->jpeg.harvest_config & (1 << i)) in jpeg_v2_5_sw_init()
128 ring = &adev->jpeg.inst[i].ring_dec; in jpeg_v2_5_sw_init()
132 r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst[i].irq, in jpeg_v2_5_sw_init()
137 adev->jpeg.internal.jpeg_pitch = mmUVD_JPEG_PITCH_INTERNAL_OFFSET; in jpeg_v2_5_sw_init()
138 adev->jpeg.inst[i].external.jpeg_pitch = SOC15_REG_OFFSET(JPEG, i, mmUVD_JPEG_PITCH); in jpeg_v2_5_sw_init()
145 * jpeg_v2_5_sw_fini - sw fini for JPEG block
149 * JPEG suspend and free up sw allocation
166 * jpeg_v2_5_hw_init - start and test JPEG block
177 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { in jpeg_v2_5_hw_init()
178 if (adev->jpeg.harvest_config & (1 << i)) in jpeg_v2_5_hw_init()
181 ring = &adev->jpeg.inst[i].ring_dec; in jpeg_v2_5_hw_init()
190 DRM_INFO("JPEG decode initialized successfully.\n"); in jpeg_v2_5_hw_init()
200 * Stop the JPEG block, mark ring as not ready any more
209 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { in jpeg_v2_5_hw_fini()
210 if (adev->jpeg.harvest_config & (1 << i)) in jpeg_v2_5_hw_fini()
213 if (adev->jpeg.cur_state != AMD_PG_STATE_GATE && in jpeg_v2_5_hw_fini()
214 RREG32_SOC15(JPEG, i, mmUVD_JRBC_STATUS)) in jpeg_v2_5_hw_fini()
222 * jpeg_v2_5_suspend - suspend JPEG block
226 * HW fini and suspend JPEG block
243 * jpeg_v2_5_resume - resume JPEG block
247 * Resume firmware and hw init JPEG block
267 data = RREG32_SOC15(JPEG, inst, mmJPEG_CGC_CTRL); in jpeg_v2_5_disable_clock_gating()
275 WREG32_SOC15(JPEG, inst, mmJPEG_CGC_CTRL, data); in jpeg_v2_5_disable_clock_gating()
277 data = RREG32_SOC15(JPEG, inst, mmJPEG_CGC_GATE); in jpeg_v2_5_disable_clock_gating()
282 WREG32_SOC15(JPEG, inst, mmJPEG_CGC_GATE, data); in jpeg_v2_5_disable_clock_gating()
284 data = RREG32_SOC15(JPEG, inst, mmJPEG_CGC_CTRL); in jpeg_v2_5_disable_clock_gating()
289 WREG32_SOC15(JPEG, inst, mmJPEG_CGC_CTRL, data); in jpeg_v2_5_disable_clock_gating()
296 data = RREG32_SOC15(JPEG, inst, mmJPEG_CGC_GATE); in jpeg_v2_5_enable_clock_gating()
302 WREG32_SOC15(JPEG, inst, mmJPEG_CGC_GATE, data); in jpeg_v2_5_enable_clock_gating()
306 * jpeg_v2_5_start - start JPEG block
310 * Setup and start the JPEG block
317 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { in jpeg_v2_5_start()
318 if (adev->jpeg.harvest_config & (1 << i)) in jpeg_v2_5_start()
321 ring = &adev->jpeg.inst[i].ring_dec; in jpeg_v2_5_start()
323 WREG32_P(SOC15_REG_OFFSET(JPEG, i, mmUVD_JPEG_POWER_STATUS), 0, in jpeg_v2_5_start()
326 /* JPEG disable CGC */ in jpeg_v2_5_start()
330 WREG32_SOC15(JPEG, i, mmJPEG_DEC_GFX8_ADDR_CONFIG, in jpeg_v2_5_start()
332 WREG32_SOC15(JPEG, i, mmJPEG_DEC_GFX10_ADDR_CONFIG, in jpeg_v2_5_start()
336 WREG32_P(SOC15_REG_OFFSET(JPEG, i, mmUVD_JMI_CNTL), 0, in jpeg_v2_5_start()
340 WREG32_P(SOC15_REG_OFFSET(JPEG, i, mmJPEG_SYS_INT_EN), in jpeg_v2_5_start()
344 WREG32_SOC15(JPEG, i, mmUVD_LMI_JRBC_RB_VMID, 0); in jpeg_v2_5_start()
345 WREG32_SOC15(JPEG, i, mmUVD_JRBC_RB_CNTL, (0x00000001L | 0x00000002L)); in jpeg_v2_5_start()
346 WREG32_SOC15(JPEG, i, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW, in jpeg_v2_5_start()
348 WREG32_SOC15(JPEG, i, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH, in jpeg_v2_5_start()
350 WREG32_SOC15(JPEG, i, mmUVD_JRBC_RB_RPTR, 0); in jpeg_v2_5_start()
351 WREG32_SOC15(JPEG, i, mmUVD_JRBC_RB_WPTR, 0); in jpeg_v2_5_start()
352 WREG32_SOC15(JPEG, i, mmUVD_JRBC_RB_CNTL, 0x00000002L); in jpeg_v2_5_start()
353 WREG32_SOC15(JPEG, i, mmUVD_JRBC_RB_SIZE, ring->ring_size / 4); in jpeg_v2_5_start()
354 ring->wptr = RREG32_SOC15(JPEG, i, mmUVD_JRBC_RB_WPTR); in jpeg_v2_5_start()
361 * jpeg_v2_5_stop - stop JPEG block
365 * stop the JPEG block
371 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { in jpeg_v2_5_stop()
372 if (adev->jpeg.harvest_config & (1 << i)) in jpeg_v2_5_stop()
376 WREG32_P(SOC15_REG_OFFSET(JPEG, i, mmUVD_JMI_CNTL), in jpeg_v2_5_stop()
383 WREG32_P(SOC15_REG_OFFSET(JPEG, i, mmUVD_JPEG_POWER_STATUS), in jpeg_v2_5_stop()
402 return RREG32_SOC15(JPEG, ring->me, mmUVD_JRBC_RB_RPTR); in jpeg_v2_5_dec_ring_get_rptr()
419 return RREG32_SOC15(JPEG, ring->me, mmUVD_JRBC_RB_WPTR); in jpeg_v2_5_dec_ring_get_wptr()
437 WREG32_SOC15(JPEG, ring->me, mmUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr)); in jpeg_v2_5_dec_ring_set_wptr()
482 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { in jpeg_v2_5_is_idle()
483 if (adev->jpeg.harvest_config & (1 << i)) in jpeg_v2_5_is_idle()
486 ret &= (((RREG32_SOC15(JPEG, i, mmUVD_JRBC_STATUS) & in jpeg_v2_5_is_idle()
499 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { in jpeg_v2_5_wait_for_idle()
500 if (adev->jpeg.harvest_config & (1 << i)) in jpeg_v2_5_wait_for_idle()
503 ret = SOC15_WAIT_ON_RREG(JPEG, i, mmUVD_JRBC_STATUS, in jpeg_v2_5_wait_for_idle()
520 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { in jpeg_v2_5_set_clockgating_state()
521 if (adev->jpeg.harvest_config & (1 << i)) in jpeg_v2_5_set_clockgating_state()
542 if(state == adev->jpeg.cur_state) in jpeg_v2_5_set_powergating_state()
551 adev->jpeg.cur_state = state; in jpeg_v2_5_set_powergating_state()
582 DRM_DEBUG("IH: JPEG TRAP\n"); in jpeg_v2_5_process_interrupt()
586 amdgpu_fence_process(&adev->jpeg.inst[ip_instance].ring_dec); in jpeg_v2_5_process_interrupt()
705 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { in jpeg_v2_5_set_dec_ring_funcs()
706 if (adev->jpeg.harvest_config & (1 << i)) in jpeg_v2_5_set_dec_ring_funcs()
709 adev->jpeg.inst[i].ring_dec.funcs = &jpeg_v2_5_dec_ring_vm_funcs; in jpeg_v2_5_set_dec_ring_funcs()
711 adev->jpeg.inst[i].ring_dec.funcs = &jpeg_v2_6_dec_ring_vm_funcs; in jpeg_v2_5_set_dec_ring_funcs()
712 adev->jpeg.inst[i].ring_dec.me = i; in jpeg_v2_5_set_dec_ring_funcs()
713 DRM_INFO("JPEG(%d) JPEG decode is enabled in VM mode\n", i); in jpeg_v2_5_set_dec_ring_funcs()
726 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { in jpeg_v2_5_set_irq_funcs()
727 if (adev->jpeg.harvest_config & (1 << i)) in jpeg_v2_5_set_irq_funcs()
730 adev->jpeg.inst[i].irq.num_types = 1; in jpeg_v2_5_set_irq_funcs()
731 adev->jpeg.inst[i].irq.funcs = &jpeg_v2_5_irq_funcs; in jpeg_v2_5_set_irq_funcs()
760 reg_value = RREG32_SOC15(JPEG, instance, mmUVD_RAS_JPEG0_STATUS); in jpeg_v2_6_query_poison_by_instance()
764 reg_value = RREG32_SOC15(JPEG, instance, mmUVD_RAS_JPEG1_STATUS); in jpeg_v2_6_query_poison_by_instance()
772 dev_info(adev->dev, "Poison detected in JPEG%d sub_block%d\n", in jpeg_v2_6_query_poison_by_instance()
782 for (inst = 0; inst < adev->jpeg.num_jpeg_inst; inst++) in jpeg_v2_6_query_ras_poison_status()
804 adev->jpeg.ras = &jpeg_v2_6_ras; in jpeg_v2_5_set_ras_funcs()
810 if (adev->jpeg.ras) { in jpeg_v2_5_set_ras_funcs()
811 amdgpu_ras_register_ras_block(adev, &adev->jpeg.ras->ras_block); in jpeg_v2_5_set_ras_funcs()
813 strcpy(adev->jpeg.ras->ras_block.ras_comm.name, "jpeg"); in jpeg_v2_5_set_ras_funcs()
814 adev->jpeg.ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__JPEG; in jpeg_v2_5_set_ras_funcs()
815 adev->jpeg.ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__POISON; in jpeg_v2_5_set_ras_funcs()
816 adev->jpeg.ras_if = &adev->jpeg.ras->ras_block.ras_comm; in jpeg_v2_5_set_ras_funcs()
819 if (!adev->jpeg.ras->ras_block.ras_late_init) in jpeg_v2_5_set_ras_funcs()
820 adev->jpeg.ras->ras_block.ras_late_init = amdgpu_ras_block_late_init; in jpeg_v2_5_set_ras_funcs()