51 	adev->jpeg.num_jpeg_inst = 1;  in jpeg_v2_0_early_init()
60  * jpeg_v2_0_sw_init - sw init for JPEG block
72 	/* JPEG TRAP */  in jpeg_v2_0_sw_init()
74 		VCN_2_0__SRCID__JPEG_DECODE, &adev->jpeg.inst->irq);  in jpeg_v2_0_sw_init()
86 	ring = &adev->jpeg.inst->ring_dec;  in jpeg_v2_0_sw_init()
90 	r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq,  in jpeg_v2_0_sw_init()
95 	adev->jpeg.internal.jpeg_pitch = mmUVD_JPEG_PITCH_INTERNAL_OFFSET;  in jpeg_v2_0_sw_init()
96 	adev->jpeg.inst->external.jpeg_pitch = SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_PITCH);  in jpeg_v2_0_sw_init()
102  * jpeg_v2_0_sw_fini - sw fini for JPEG block
106  * JPEG suspend and free up sw allocation
123  * jpeg_v2_0_hw_init - start and test JPEG block
131 	struct amdgpu_ring *ring = &adev->jpeg.inst->ring_dec;  in jpeg_v2_0_hw_init()
139 		DRM_INFO("JPEG decode initialized successfully.\n");  in jpeg_v2_0_hw_init()
149  * Stop the JPEG block, mark ring as not ready any more
157 	if (adev->jpeg.cur_state != AMD_PG_STATE_GATE &&  in jpeg_v2_0_hw_fini()
158 	      RREG32_SOC15(JPEG, 0, mmUVD_JRBC_STATUS))  in jpeg_v2_0_hw_fini()
165  * jpeg_v2_0_suspend - suspend JPEG block
169  * HW fini and suspend JPEG block
186  * jpeg_v2_0_resume - resume JPEG block
190  * Resume firmware and hw init JPEG block
213 		WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_PGFSM_CONFIG), data);  in jpeg_v2_0_disable_power_gating()
215 		r = SOC15_WAIT_ON_RREG(JPEG, 0,  in jpeg_v2_0_disable_power_gating()
220 			DRM_ERROR("amdgpu: JPEG disable power gating failed\n");  in jpeg_v2_0_disable_power_gating()
226 	data = RREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS)) & ~0x1;  in jpeg_v2_0_disable_power_gating()
227 	WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS), data);  in jpeg_v2_0_disable_power_gating()
238 		data = RREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS));  in jpeg_v2_0_enable_power_gating()
241 		WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS), data);  in jpeg_v2_0_enable_power_gating()
244 		WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_PGFSM_CONFIG), data);  in jpeg_v2_0_enable_power_gating()
246 		r = SOC15_WAIT_ON_RREG(JPEG, 0, mmUVD_PGFSM_STATUS,  in jpeg_v2_0_enable_power_gating()
251 			DRM_ERROR("amdgpu: JPEG enable power gating failed\n");  in jpeg_v2_0_enable_power_gating()
263 	data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL);  in jpeg_v2_0_disable_clock_gating()
271 	WREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL, data);  in jpeg_v2_0_disable_clock_gating()
273 	data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE);  in jpeg_v2_0_disable_clock_gating()
279 	WREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE, data);  in jpeg_v2_0_disable_clock_gating()
286 	data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL);  in jpeg_v2_0_enable_clock_gating()
294 	WREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL, data);  in jpeg_v2_0_enable_clock_gating()
296 	data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE);  in jpeg_v2_0_enable_clock_gating()
302 	WREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE, data);  in jpeg_v2_0_enable_clock_gating()
306  * jpeg_v2_0_start - start JPEG block
310  * Setup and start the JPEG block
314 	struct amdgpu_ring *ring = &adev->jpeg.inst->ring_dec;  in jpeg_v2_0_start()
325 	/* JPEG disable CGC */  in jpeg_v2_0_start()
328 	WREG32_SOC15(JPEG, 0, mmJPEG_DEC_GFX10_ADDR_CONFIG, adev->gfx.config.gb_addr_config);  in jpeg_v2_0_start()
331 	WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JMI_CNTL), 0,  in jpeg_v2_0_start()
335 	WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmJPEG_SYS_INT_EN),  in jpeg_v2_0_start()
339 	WREG32_SOC15(JPEG, 0, mmUVD_LMI_JRBC_RB_VMID, 0);  in jpeg_v2_0_start()
340 	WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_CNTL, (0x00000001L | 0x00000002L));  in jpeg_v2_0_start()
341 	WREG32_SOC15(JPEG, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW,  in jpeg_v2_0_start()
343 	WREG32_SOC15(JPEG, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH,  in jpeg_v2_0_start()
345 	WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_RPTR, 0);  in jpeg_v2_0_start()
346 	WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR, 0);  in jpeg_v2_0_start()
347 	WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_CNTL, 0x00000002L);  in jpeg_v2_0_start()
348 	WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_SIZE, ring->ring_size / 4);  in jpeg_v2_0_start()
349 	ring->wptr = RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR);  in jpeg_v2_0_start()
355  * jpeg_v2_0_stop - stop JPEG block
359  * stop the JPEG block
366 	WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JMI_CNTL),  in jpeg_v2_0_stop()
370 	/* enable JPEG CGC */  in jpeg_v2_0_stop()
395 	return RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_RPTR);  in jpeg_v2_0_dec_ring_get_rptr()
412 		return RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR);  in jpeg_v2_0_dec_ring_get_wptr()
430 		WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr));  in jpeg_v2_0_dec_ring_set_wptr()
662 	return ((RREG32_SOC15(JPEG, 0, mmUVD_JRBC_STATUS) &  in jpeg_v2_0_is_idle()
672 	ret = SOC15_WAIT_ON_RREG(JPEG, 0, mmUVD_JRBC_STATUS, UVD_JRBC_STATUS__RB_JOB_DONE_MASK,  in jpeg_v2_0_wait_for_idle()
701 	if (state == adev->jpeg.cur_state)  in jpeg_v2_0_set_powergating_state()
710 		adev->jpeg.cur_state = state;  in jpeg_v2_0_set_powergating_state()
727 	DRM_DEBUG("IH: JPEG TRAP\n");  in jpeg_v2_0_process_interrupt()
731 		amdgpu_fence_process(&adev->jpeg.inst->ring_dec);  in jpeg_v2_0_process_interrupt()
794 	adev->jpeg.inst->ring_dec.funcs = &jpeg_v2_0_dec_ring_vm_funcs;  in jpeg_v2_0_set_dec_ring_funcs()
795 	DRM_INFO("JPEG decode is enabled in VM mode\n");  in jpeg_v2_0_set_dec_ring_funcs()
805 	adev->jpeg.inst->irq.num_types = 1;  in jpeg_v2_0_set_irq_funcs()
806 	adev->jpeg.inst->irq.funcs = &jpeg_v2_0_irq_funcs;  in jpeg_v2_0_set_irq_funcs()