1203 		adev->umc.funcs = &umc_v6_0_funcs;  in gmc_v9_0_set_umc_funcs()
1206 		adev->umc.max_ras_err_cnt_per_query = UMC_V6_1_TOTAL_CHANNEL_NUM;  in gmc_v9_0_set_umc_funcs()
1207 		adev->umc.channel_inst_num = UMC_V6_1_CHANNEL_INSTANCE_NUM;  in gmc_v9_0_set_umc_funcs()
1208 		adev->umc.umc_inst_num = UMC_V6_1_UMC_INSTANCE_NUM;  in gmc_v9_0_set_umc_funcs()
1209 		adev->umc.channel_offs = UMC_V6_1_PER_CHANNEL_OFFSET_VG20;  in gmc_v9_0_set_umc_funcs()
1210 		adev->umc.channel_idx_tbl = &umc_v6_1_channel_idx_tbl[0][0];  in gmc_v9_0_set_umc_funcs()
1211 		adev->umc.ras = &umc_v6_1_ras;  in gmc_v9_0_set_umc_funcs()
1214 		adev->umc.max_ras_err_cnt_per_query = UMC_V6_1_TOTAL_CHANNEL_NUM;  in gmc_v9_0_set_umc_funcs()
1215 		adev->umc.channel_inst_num = UMC_V6_1_CHANNEL_INSTANCE_NUM;  in gmc_v9_0_set_umc_funcs()
1216 		adev->umc.umc_inst_num = UMC_V6_1_UMC_INSTANCE_NUM;  in gmc_v9_0_set_umc_funcs()
1217 		adev->umc.channel_offs = UMC_V6_1_PER_CHANNEL_OFFSET_ARCT;  in gmc_v9_0_set_umc_funcs()
1218 		adev->umc.channel_idx_tbl = &umc_v6_1_channel_idx_tbl[0][0];  in gmc_v9_0_set_umc_funcs()
1219 		adev->umc.ras = &umc_v6_1_ras;  in gmc_v9_0_set_umc_funcs()
1222 		adev->umc.max_ras_err_cnt_per_query =  in gmc_v9_0_set_umc_funcs()
1224 		adev->umc.channel_inst_num = UMC_V6_7_CHANNEL_INSTANCE_NUM;  in gmc_v9_0_set_umc_funcs()
1225 		adev->umc.umc_inst_num = UMC_V6_7_UMC_INSTANCE_NUM;  in gmc_v9_0_set_umc_funcs()
1226 		adev->umc.channel_offs = UMC_V6_7_PER_CHANNEL_OFFSET;  in gmc_v9_0_set_umc_funcs()
1228 			adev->umc.ras = &umc_v6_7_ras;  in gmc_v9_0_set_umc_funcs()
1230 			adev->umc.channel_idx_tbl = &umc_v6_7_channel_idx_tbl_first[0][0];  in gmc_v9_0_set_umc_funcs()
1232 			adev->umc.channel_idx_tbl = &umc_v6_7_channel_idx_tbl_second[0][0];  in gmc_v9_0_set_umc_funcs()
1238 	if (adev->umc.ras) {  in gmc_v9_0_set_umc_funcs()
1239 		amdgpu_ras_register_ras_block(adev, &adev->umc.ras->ras_block);  in gmc_v9_0_set_umc_funcs()
1241 		strcpy(adev->umc.ras->ras_block.ras_comm.name, "umc");  in gmc_v9_0_set_umc_funcs()
1242 		adev->umc.ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__UMC;  in gmc_v9_0_set_umc_funcs()
1243 		adev->umc.ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;  in gmc_v9_0_set_umc_funcs()
1244 		adev->umc.ras_if = &adev->umc.ras->ras_block.ras_comm;  in gmc_v9_0_set_umc_funcs()
1247 		if (!adev->umc.ras->ras_block.ras_late_init)  in gmc_v9_0_set_umc_funcs()
1248 				adev->umc.ras->ras_block.ras_late_init = amdgpu_umc_ras_late_init;  in gmc_v9_0_set_umc_funcs()
1251 		if (!adev->umc.ras->ras_block.ras_cb)  in gmc_v9_0_set_umc_funcs()
1252 			adev->umc.ras->ras_block.ras_cb = amdgpu_umc_process_ras_data_cb;  in gmc_v9_0_set_umc_funcs()
1855 	if (adev->umc.funcs && adev->umc.funcs->init_registers)  in gmc_v9_0_hw_init()
1856 		adev->umc.funcs->init_registers(adev);  in gmc_v9_0_hw_init()