267 	err = request_firmware(&adev->gmc.fw, fw_name, adev->dev);  in gmc_v8_0_init_microcode()
270 	err = amdgpu_ucode_validate(adev->gmc.fw);  in gmc_v8_0_init_microcode()
275 		release_firmware(adev->gmc.fw);  in gmc_v8_0_init_microcode()
276 		adev->gmc.fw = NULL;  in gmc_v8_0_init_microcode()
305 	if (!adev->gmc.fw)  in gmc_v8_0_tonga_mc_load_microcode()
308 	hdr = (const struct mc_firmware_header_v1_0 *)adev->gmc.fw->data;  in gmc_v8_0_tonga_mc_load_microcode()
311 	adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version);  in gmc_v8_0_tonga_mc_load_microcode()
314 		(adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));  in gmc_v8_0_tonga_mc_load_microcode()
317 		(adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));  in gmc_v8_0_tonga_mc_load_microcode()
374 	if (!adev->gmc.fw)  in gmc_v8_0_polaris_mc_load_microcode()
377 	hdr = (const struct mc_firmware_header_v1_0 *)adev->gmc.fw->data;  in gmc_v8_0_polaris_mc_load_microcode()
380 	adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version);  in gmc_v8_0_polaris_mc_load_microcode()
383 		(adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));  in gmc_v8_0_polaris_mc_load_microcode()
386 		(adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));  in gmc_v8_0_polaris_mc_load_microcode()
473 	       adev->gmc.vram_start >> 12);  in gmc_v8_0_mc_program()
475 	       adev->gmc.vram_end >> 12);  in gmc_v8_0_mc_program()
480 		tmp = ((adev->gmc.vram_end >> 24) & 0xFFFF) << 16;  in gmc_v8_0_mc_program()
481 		tmp |= ((adev->gmc.vram_start >> 24) & 0xFFFF);  in gmc_v8_0_mc_program()
484 		WREG32(mmHDP_NONSURFACE_BASE, (adev->gmc.vram_start >> 8));  in gmc_v8_0_mc_program()
520 	adev->gmc.vram_width = amdgpu_atombios_get_vram_width(adev);  in gmc_v8_0_mc_init()
521 	if (!adev->gmc.vram_width) {  in gmc_v8_0_mc_init()
562 		adev->gmc.vram_width = numchan * chansize;  in gmc_v8_0_mc_init()
572 	adev->gmc.mc_vram_size = tmp * 1024ULL * 1024ULL;  in gmc_v8_0_mc_init()
573 	adev->gmc.real_vram_size = adev->gmc.mc_vram_size;  in gmc_v8_0_mc_init()
580 	adev->gmc.aper_base = pci_resource_start(adev->pdev, 0);  in gmc_v8_0_mc_init()
581 	adev->gmc.aper_size = pci_resource_len(adev->pdev, 0);  in gmc_v8_0_mc_init()
585 		adev->gmc.aper_base = ((u64)RREG32(mmMC_VM_FB_OFFSET)) << 22;  in gmc_v8_0_mc_init()
586 		adev->gmc.aper_size = adev->gmc.real_vram_size;  in gmc_v8_0_mc_init()
591 	adev->gmc.visible_vram_size = adev->gmc.aper_size;  in gmc_v8_0_mc_init()
592 	if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size)  in gmc_v8_0_mc_init()
593 		adev->gmc.visible_vram_size = adev->gmc.real_vram_size;  in gmc_v8_0_mc_init()
603 			adev->gmc.gart_size = 256ULL << 20;  in gmc_v8_0_mc_init()
609 			adev->gmc.gart_size = 1024ULL << 20;  in gmc_v8_0_mc_init()
613 		adev->gmc.gart_size = (u64)amdgpu_gart_size << 20;  in gmc_v8_0_mc_init()
616 	adev->gmc.gart_size += adev->pm.smu_prv_buffer_size;  in gmc_v8_0_mc_init()
617 	gmc_v8_0_vram_gtt_location(adev, &adev->gmc);  in gmc_v8_0_mc_init()
779 	if (enable && !adev->gmc.prt_warning) {  in gmc_v8_0_set_prt()
781 		adev->gmc.prt_warning = true;  in gmc_v8_0_set_prt()
895 	WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->gmc.gart_start >> 12);  in gmc_v8_0_gart_enable()
896 	WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->gmc.gart_end >> 12);  in gmc_v8_0_gart_enable()
951 		 (unsigned)(adev->gmc.gart_size >> 20),  in gmc_v8_0_gart_enable()
1060 	adev->gmc.shared_aperture_start = 0x2000000000000000ULL;  in gmc_v8_0_early_init()
1061 	adev->gmc.shared_aperture_end =  in gmc_v8_0_early_init()
1062 		adev->gmc.shared_aperture_start + (4ULL << 30) - 1;  in gmc_v8_0_early_init()
1063 	adev->gmc.private_aperture_start =  in gmc_v8_0_early_init()
1064 		adev->gmc.shared_aperture_end + 1;  in gmc_v8_0_early_init()
1065 	adev->gmc.private_aperture_end =  in gmc_v8_0_early_init()
1066 		adev->gmc.private_aperture_start + (4ULL << 30) - 1;  in gmc_v8_0_early_init()
1076 		return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0);  in gmc_v8_0_late_init()
1108 		adev->gmc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;  in gmc_v8_0_sw_init()
1118 		adev->gmc.vram_type = gmc_v8_0_convert_vram_type(tmp);  in gmc_v8_0_sw_init()
1121 …_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_GFX_PAGE_INV_FAULT, &adev->gmc.vm_fault);  in gmc_v8_0_sw_init()
1125 …_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_GFX_MEM_PROT_FAULT, &adev->gmc.vm_fault);  in gmc_v8_0_sw_init()
1139 	adev->gmc.mc_mask = 0xffffffffffULL; /* 40 bit MC */  in gmc_v8_0_sw_init()
1188 	adev->gmc.vm_fault_info = kmalloc(sizeof(struct kfd_vm_fault_info),  in gmc_v8_0_sw_init()
1190 	if (!adev->gmc.vm_fault_info)  in gmc_v8_0_sw_init()
1192 	atomic_set(&adev->gmc.vm_fault_info_updated, 0);  in gmc_v8_0_sw_init()
1203 	kfree(adev->gmc.vm_fault_info);  in gmc_v8_0_sw_fini()
1206 	release_firmware(adev->gmc.fw);  in gmc_v8_0_sw_fini()
1207 	adev->gmc.fw = NULL;  in gmc_v8_0_sw_fini()
1251 	amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0);  in gmc_v8_0_hw_fini()
1331 		adev->gmc.srbm_soft_reset = srbm_soft_reset;  in gmc_v8_0_check_soft_reset()
1334 		adev->gmc.srbm_soft_reset = 0;  in gmc_v8_0_check_soft_reset()
1343 	if (!adev->gmc.srbm_soft_reset)  in gmc_v8_0_pre_soft_reset()
1359 	if (!adev->gmc.srbm_soft_reset)  in gmc_v8_0_soft_reset()
1361 	srbm_soft_reset = adev->gmc.srbm_soft_reset;  in gmc_v8_0_soft_reset()
1389 	if (!adev->gmc.srbm_soft_reset)  in gmc_v8_0_post_soft_reset()
1483 		&& !atomic_read(&adev->gmc.vm_fault_info_updated)) {  in gmc_v8_0_process_interrupt()
1484 		struct kfd_vm_fault_info *info = adev->gmc.vm_fault_info;  in gmc_v8_0_process_interrupt()
1500 		atomic_set(&adev->gmc.vm_fault_info_updated, 1);  in gmc_v8_0_process_interrupt()
1750 	adev->gmc.gmc_funcs = &gmc_v8_0_gmc_funcs;  in gmc_v8_0_set_gmc_funcs()
1755 	adev->gmc.vm_fault.num_types = 1;  in gmc_v8_0_set_irq_funcs()
1756 	adev->gmc.vm_fault.funcs = &gmc_v8_0_irq_funcs;  in gmc_v8_0_set_irq_funcs()