188 		WREG32(mmBIF_FB_EN, 0);  in gmc_v8_0_mc_stop()
192 		WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout);  in gmc_v8_0_mc_stop()
205 	WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp);  in gmc_v8_0_mc_resume()
209 	WREG32(mmBIF_FB_EN, tmp);  in gmc_v8_0_mc_resume()
250 			WREG32(mmMC_SEQ_IO_DEBUG_INDEX, ixMC_IO_DEBUG_UP_159);  in gmc_v8_0_init_microcode()
323 		WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);  in gmc_v8_0_tonga_mc_load_microcode()
324 		WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010);  in gmc_v8_0_tonga_mc_load_microcode()
328 			WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++));  in gmc_v8_0_tonga_mc_load_microcode()
329 			WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++));  in gmc_v8_0_tonga_mc_load_microcode()
333 			WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++));  in gmc_v8_0_tonga_mc_load_microcode()
336 		WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);  in gmc_v8_0_tonga_mc_load_microcode()
337 		WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004);  in gmc_v8_0_tonga_mc_load_microcode()
338 		WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001);  in gmc_v8_0_tonga_mc_load_microcode()
390 	WREG32(mmMC_SEQ_MISC0, data);  in gmc_v8_0_polaris_mc_load_microcode()
394 		WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++));  in gmc_v8_0_polaris_mc_load_microcode()
395 		WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++));  in gmc_v8_0_polaris_mc_load_microcode()
398 	WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);  in gmc_v8_0_polaris_mc_load_microcode()
399 	WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010);  in gmc_v8_0_polaris_mc_load_microcode()
403 		WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++));  in gmc_v8_0_polaris_mc_load_microcode()
406 	WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);  in gmc_v8_0_polaris_mc_load_microcode()
407 	WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004);  in gmc_v8_0_polaris_mc_load_microcode()
408 	WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001);  in gmc_v8_0_polaris_mc_load_microcode()
449 		WREG32((0xb05 + j), 0x00000000);  in gmc_v8_0_mc_program()
450 		WREG32((0xb06 + j), 0x00000000);  in gmc_v8_0_mc_program()
451 		WREG32((0xb07 + j), 0x00000000);  in gmc_v8_0_mc_program()
452 		WREG32((0xb08 + j), 0x00000000);  in gmc_v8_0_mc_program()
453 		WREG32((0xb09 + j), 0x00000000);  in gmc_v8_0_mc_program()
455 	WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0);  in gmc_v8_0_mc_program()
464 		WREG32(mmVGA_HDP_CONTROL, tmp);  in gmc_v8_0_mc_program()
469 		WREG32(mmVGA_RENDER_CONTROL, tmp);  in gmc_v8_0_mc_program()
472 	WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,  in gmc_v8_0_mc_program()
474 	WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,  in gmc_v8_0_mc_program()
476 	WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,  in gmc_v8_0_mc_program()
482 		WREG32(mmMC_VM_FB_LOCATION, tmp);  in gmc_v8_0_mc_program()
484 		WREG32(mmHDP_NONSURFACE_BASE, (adev->gmc.vram_start >> 8));  in gmc_v8_0_mc_program()
485 		WREG32(mmHDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));  in gmc_v8_0_mc_program()
486 		WREG32(mmHDP_NONSURFACE_SIZE, 0x3FFFFFFF);  in gmc_v8_0_mc_program()
489 	WREG32(mmMC_VM_AGP_BASE, 0);  in gmc_v8_0_mc_program()
490 	WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF);  in gmc_v8_0_mc_program()
491 	WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF);  in gmc_v8_0_mc_program()
496 	WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK);  in gmc_v8_0_mc_program()
500 	WREG32(mmHDP_MISC_CNTL, tmp);  in gmc_v8_0_mc_program()
503 	WREG32(mmHDP_HOST_PATH_CNTL, tmp);  in gmc_v8_0_mc_program()
647 			WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);  in gmc_v8_0_flush_gpu_tlb_pasid()
678 	WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);  in gmc_v8_0_flush_gpu_tlb()
766 	WREG32(mmVM_CONTEXT1_CNTL, tmp);  in gmc_v8_0_set_fault_enable_default()
799 	WREG32(mmVM_PRT_CNTL, tmp);  in gmc_v8_0_set_prt()
806 		WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, low);  in gmc_v8_0_set_prt()
807 		WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, low);  in gmc_v8_0_set_prt()
808 		WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, low);  in gmc_v8_0_set_prt()
809 		WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, low);  in gmc_v8_0_set_prt()
810 		WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, high);  in gmc_v8_0_set_prt()
811 		WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, high);  in gmc_v8_0_set_prt()
812 		WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, high);  in gmc_v8_0_set_prt()
813 		WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, high);  in gmc_v8_0_set_prt()
815 		WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, 0xfffffff);  in gmc_v8_0_set_prt()
816 		WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, 0xfffffff);  in gmc_v8_0_set_prt()
817 		WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, 0xfffffff);  in gmc_v8_0_set_prt()
818 		WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, 0xfffffff);  in gmc_v8_0_set_prt()
819 		WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, 0x0);  in gmc_v8_0_set_prt()
820 		WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, 0x0);  in gmc_v8_0_set_prt()
821 		WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, 0x0);  in gmc_v8_0_set_prt()
822 		WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, 0x0);  in gmc_v8_0_set_prt()
857 	WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);  in gmc_v8_0_gart_enable()
867 	WREG32(mmVM_L2_CNTL, tmp);  in gmc_v8_0_gart_enable()
871 	WREG32(mmVM_L2_CNTL2, tmp);  in gmc_v8_0_gart_enable()
878 	WREG32(mmVM_L2_CNTL3, tmp);  in gmc_v8_0_gart_enable()
893 	WREG32(mmVM_L2_CNTL4, tmp);  in gmc_v8_0_gart_enable()
895 	WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->gmc.gart_start >> 12);  in gmc_v8_0_gart_enable()
896 	WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->gmc.gart_end >> 12);  in gmc_v8_0_gart_enable()
897 	WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, table_addr >> 12);  in gmc_v8_0_gart_enable()
898 	WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,  in gmc_v8_0_gart_enable()
900 	WREG32(mmVM_CONTEXT0_CNTL2, 0);  in gmc_v8_0_gart_enable()
905 	WREG32(mmVM_CONTEXT0_CNTL, tmp);  in gmc_v8_0_gart_enable()
907 	WREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR, 0);  in gmc_v8_0_gart_enable()
908 	WREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR, 0);  in gmc_v8_0_gart_enable()
909 	WREG32(mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET, 0);  in gmc_v8_0_gart_enable()
916 	WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);  in gmc_v8_0_gart_enable()
917 	WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1);  in gmc_v8_0_gart_enable()
920 			WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i,  in gmc_v8_0_gart_enable()
923 			WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8,  in gmc_v8_0_gart_enable()
928 	WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,  in gmc_v8_0_gart_enable()
930 	WREG32(mmVM_CONTEXT1_CNTL2, 4);  in gmc_v8_0_gart_enable()
943 	WREG32(mmVM_CONTEXT1_CNTL, tmp);  in gmc_v8_0_gart_enable()
985 	WREG32(mmVM_CONTEXT0_CNTL, 0);  in gmc_v8_0_gart_disable()
986 	WREG32(mmVM_CONTEXT1_CNTL, 0);  in gmc_v8_0_gart_disable()
992 	WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);  in gmc_v8_0_gart_disable()
996 	WREG32(mmVM_L2_CNTL, tmp);  in gmc_v8_0_gart_disable()
997 	WREG32(mmVM_L2_CNTL2, 0);  in gmc_v8_0_gart_disable()
1369 		WREG32(mmSRBM_SOFT_RESET, tmp);  in gmc_v8_0_soft_reset()
1375 		WREG32(mmSRBM_SOFT_RESET, tmp);  in gmc_v8_0_soft_reset()
1415 		WREG32(mmVM_CONTEXT0_CNTL, tmp);  in gmc_v8_0_vm_fault_interrupt_state()
1419 		WREG32(mmVM_CONTEXT1_CNTL, tmp);  in gmc_v8_0_vm_fault_interrupt_state()
1425 		WREG32(mmVM_CONTEXT0_CNTL, tmp);  in gmc_v8_0_vm_fault_interrupt_state()
1429 		WREG32(mmVM_CONTEXT1_CNTL, tmp);  in gmc_v8_0_vm_fault_interrupt_state()
1514 		WREG32(mmMC_HUB_MISC_HUB_CG, data);  in fiji_update_mc_medium_grain_clock_gating()
1518 		WREG32(mmMC_HUB_MISC_SIP_CG, data);  in fiji_update_mc_medium_grain_clock_gating()
1522 		WREG32(mmMC_HUB_MISC_VM_CG, data);  in fiji_update_mc_medium_grain_clock_gating()
1526 		WREG32(mmMC_XPB_CLK_GAT, data);  in fiji_update_mc_medium_grain_clock_gating()
1530 		WREG32(mmATC_MISC_CG, data);  in fiji_update_mc_medium_grain_clock_gating()
1534 		WREG32(mmMC_CITF_MISC_WR_CG, data);  in fiji_update_mc_medium_grain_clock_gating()
1538 		WREG32(mmMC_CITF_MISC_RD_CG, data);  in fiji_update_mc_medium_grain_clock_gating()
1542 		WREG32(mmMC_CITF_MISC_VM_CG, data);  in fiji_update_mc_medium_grain_clock_gating()
1546 		WREG32(mmVM_L2_CG, data);  in fiji_update_mc_medium_grain_clock_gating()
1550 		WREG32(mmMC_HUB_MISC_HUB_CG, data);  in fiji_update_mc_medium_grain_clock_gating()
1554 		WREG32(mmMC_HUB_MISC_SIP_CG, data);  in fiji_update_mc_medium_grain_clock_gating()
1558 		WREG32(mmMC_HUB_MISC_VM_CG, data);  in fiji_update_mc_medium_grain_clock_gating()
1562 		WREG32(mmMC_XPB_CLK_GAT, data);  in fiji_update_mc_medium_grain_clock_gating()
1566 		WREG32(mmATC_MISC_CG, data);  in fiji_update_mc_medium_grain_clock_gating()
1570 		WREG32(mmMC_CITF_MISC_WR_CG, data);  in fiji_update_mc_medium_grain_clock_gating()
1574 		WREG32(mmMC_CITF_MISC_RD_CG, data);  in fiji_update_mc_medium_grain_clock_gating()
1578 		WREG32(mmMC_CITF_MISC_VM_CG, data);  in fiji_update_mc_medium_grain_clock_gating()
1582 		WREG32(mmVM_L2_CG, data);  in fiji_update_mc_medium_grain_clock_gating()
1594 		WREG32(mmMC_HUB_MISC_HUB_CG, data);  in fiji_update_mc_light_sleep()
1598 		WREG32(mmMC_HUB_MISC_SIP_CG, data);  in fiji_update_mc_light_sleep()
1602 		WREG32(mmMC_HUB_MISC_VM_CG, data);  in fiji_update_mc_light_sleep()
1606 		WREG32(mmMC_XPB_CLK_GAT, data);  in fiji_update_mc_light_sleep()
1610 		WREG32(mmATC_MISC_CG, data);  in fiji_update_mc_light_sleep()
1614 		WREG32(mmMC_CITF_MISC_WR_CG, data);  in fiji_update_mc_light_sleep()
1618 		WREG32(mmMC_CITF_MISC_RD_CG, data);  in fiji_update_mc_light_sleep()
1622 		WREG32(mmMC_CITF_MISC_VM_CG, data);  in fiji_update_mc_light_sleep()
1626 		WREG32(mmVM_L2_CG, data);  in fiji_update_mc_light_sleep()
1630 		WREG32(mmMC_HUB_MISC_HUB_CG, data);  in fiji_update_mc_light_sleep()
1634 		WREG32(mmMC_HUB_MISC_SIP_CG, data);  in fiji_update_mc_light_sleep()
1638 		WREG32(mmMC_HUB_MISC_VM_CG, data);  in fiji_update_mc_light_sleep()
1642 		WREG32(mmMC_XPB_CLK_GAT, data);  in fiji_update_mc_light_sleep()
1646 		WREG32(mmATC_MISC_CG, data);  in fiji_update_mc_light_sleep()
1650 		WREG32(mmMC_CITF_MISC_WR_CG, data);  in fiji_update_mc_light_sleep()
1654 		WREG32(mmMC_CITF_MISC_RD_CG, data);  in fiji_update_mc_light_sleep()
1658 		WREG32(mmMC_CITF_MISC_VM_CG, data);  in fiji_update_mc_light_sleep()
1662 		WREG32(mmVM_L2_CG, data);  in fiji_update_mc_light_sleep()