96 	blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL);  in gmc_v7_0_mc_stop()
114 	tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL);  in gmc_v7_0_mc_resume()
203 	running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN);  in gmc_v7_0_mc_load_microcode()
226 			if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),  in gmc_v7_0_mc_load_microcode()
232 			if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),  in gmc_v7_0_mc_load_microcode()
245 	u64 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF;  in gmc_v7_0_vram_gtt_location()
280 		tmp = RREG32(mmVGA_HDP_CONTROL);  in gmc_v7_0_mc_program()
285 		tmp = RREG32(mmVGA_RENDER_CONTROL);  in gmc_v7_0_mc_program()
305 	tmp = RREG32(mmHDP_MISC_CNTL);  in gmc_v7_0_mc_program()
309 	tmp = RREG32(mmHDP_HOST_PATH_CNTL);  in gmc_v7_0_mc_program()
332 		tmp = RREG32(mmMC_ARB_RAMCFG);  in gmc_v7_0_mc_init()
338 		tmp = RREG32(mmMC_SHARED_CHMAP);  in gmc_v7_0_mc_init()
372 	adev->gmc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;  in gmc_v7_0_mc_init()
373 	adev->gmc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;  in gmc_v7_0_mc_init()
387 		adev->gmc.aper_base = ((u64)RREG32(mmMC_VM_FB_OFFSET)) << 22;  in gmc_v7_0_mc_init()
446 		tmp = RREG32(mmATC_VMID0_PASID_MAPPING + vmid);  in gmc_v7_0_flush_gpu_tlb_pasid()
450 			RREG32(mmVM_INVALIDATE_RESPONSE);  in gmc_v7_0_flush_gpu_tlb_pasid()
530 	tmp = RREG32(mmVM_CONTEXT1_CNTL);  in gmc_v7_0_set_fault_enable_default()
561 	tmp = RREG32(mmVM_PRT_CNTL);  in gmc_v7_0_set_prt()
628 	tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);  in gmc_v7_0_gart_enable()
636 	tmp = RREG32(mmVM_L2_CNTL);  in gmc_v7_0_gart_enable()
650 	tmp = RREG32(mmVM_L2_CNTL3);  in gmc_v7_0_gart_enable()
662 	tmp = RREG32(mmVM_CONTEXT0_CNTL);  in gmc_v7_0_gart_enable()
692 	tmp = RREG32(mmVM_CONTEXT1_CNTL);  in gmc_v7_0_gart_enable()
704 		tmp = RREG32(mmCHUB_CONTROL);  in gmc_v7_0_gart_enable()
748 	tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);  in gmc_v7_0_gart_disable()
754 	tmp = RREG32(mmVM_L2_CNTL);  in gmc_v7_0_gart_disable()
835 		orig = data = RREG32(mc_cg_registers[i]);  in gmc_v7_0_enable_mc_ls()
852 		orig = data = RREG32(mc_cg_registers[i]);  in gmc_v7_0_enable_mc_mgcg()
890 	orig = data = RREG32(mmHDP_HOST_PATH_CNTL);  in gmc_v7_0_enable_hdp_mgcg()
906 	orig = data = RREG32(mmHDP_MEM_POWER_LS);  in gmc_v7_0_enable_hdp_ls()
969 	u32 d1vga_control = RREG32(mmD1VGA_CONTROL);  in gmc_v7_0_get_vbios_fb_size()
975 		u32 viewport = RREG32(mmVIEWPORT_SIZE);  in gmc_v7_0_get_vbios_fb_size()
994 		u32 tmp = RREG32(mmMC_SEQ_MISC0);  in gmc_v7_0_sw_init()
1058 		u64 tmp = RREG32(mmMC_VM_FB_OFFSET);  in gmc_v7_0_sw_init()
1153 	u32 tmp = RREG32(mmSRBM_STATUS);  in gmc_v7_0_is_idle()
1170 		tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK |  in gmc_v7_0_wait_for_idle()
1187 	u32 tmp = RREG32(mmSRBM_STATUS);  in gmc_v7_0_soft_reset()
1207 		tmp = RREG32(mmSRBM_SOFT_RESET);  in gmc_v7_0_soft_reset()
1211 		tmp = RREG32(mmSRBM_SOFT_RESET);  in gmc_v7_0_soft_reset()
1217 		tmp = RREG32(mmSRBM_SOFT_RESET);  in gmc_v7_0_soft_reset()
1245 		tmp = RREG32(mmVM_CONTEXT0_CNTL);  in gmc_v7_0_vm_fault_interrupt_state()
1249 		tmp = RREG32(mmVM_CONTEXT1_CNTL);  in gmc_v7_0_vm_fault_interrupt_state()
1255 		tmp = RREG32(mmVM_CONTEXT0_CNTL);  in gmc_v7_0_vm_fault_interrupt_state()
1259 		tmp = RREG32(mmVM_CONTEXT1_CNTL);  in gmc_v7_0_vm_fault_interrupt_state()
1276 	addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR);  in gmc_v7_0_process_interrupt()
1277 	status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS);  in gmc_v7_0_process_interrupt()
1278 	mc_client = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT);  in gmc_v7_0_process_interrupt()