549 		adev->umc.channel_inst_num = UMC_V8_10_CHANNEL_INSTANCE_NUM;  in gmc_v11_0_set_umc_funcs()
550 		adev->umc.umc_inst_num = UMC_V8_10_UMC_INSTANCE_NUM;  in gmc_v11_0_set_umc_funcs()
551 		adev->umc.node_inst_num = adev->gmc.num_umc;  in gmc_v11_0_set_umc_funcs()
552 		adev->umc.max_ras_err_cnt_per_query = UMC_V8_10_TOTAL_CHANNEL_NUM(adev);  in gmc_v11_0_set_umc_funcs()
553 		adev->umc.channel_offs = UMC_V8_10_PER_CHANNEL_OFFSET;  in gmc_v11_0_set_umc_funcs()
554 		adev->umc.channel_idx_tbl = &umc_v8_10_channel_idx_tbl[0][0][0];  in gmc_v11_0_set_umc_funcs()
555 		adev->umc.ras = &umc_v8_10_ras;  in gmc_v11_0_set_umc_funcs()
563 	if (adev->umc.ras) {  in gmc_v11_0_set_umc_funcs()
564 		amdgpu_ras_register_ras_block(adev, &adev->umc.ras->ras_block);  in gmc_v11_0_set_umc_funcs()
566 		strcpy(adev->umc.ras->ras_block.ras_comm.name, "umc");  in gmc_v11_0_set_umc_funcs()
567 		adev->umc.ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__UMC;  in gmc_v11_0_set_umc_funcs()
568 		adev->umc.ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;  in gmc_v11_0_set_umc_funcs()
569 		adev->umc.ras_if = &adev->umc.ras->ras_block.ras_comm;  in gmc_v11_0_set_umc_funcs()
572 		if (!adev->umc.ras->ras_block.ras_late_init)  in gmc_v11_0_set_umc_funcs()
573 			adev->umc.ras->ras_block.ras_late_init = amdgpu_umc_ras_late_init;  in gmc_v11_0_set_umc_funcs()
576 		if (!adev->umc.ras->ras_block.ras_cb)  in gmc_v11_0_set_umc_funcs()
577 			adev->umc.ras->ras_block.ras_cb = amdgpu_umc_process_ras_data_cb;  in gmc_v11_0_set_umc_funcs()
905 	if (adev->umc.funcs && adev->umc.funcs->init_registers)  in gmc_v11_0_hw_init()
906 		adev->umc.funcs->init_registers(adev);  in gmc_v11_0_hw_init()