140 	adev->gmc.vm_fault.num_types = 1;  in gmc_v11_0_set_irq_funcs()
141 	adev->gmc.vm_fault.funcs = &gmc_v11_0_irq_funcs;  in gmc_v11_0_set_irq_funcs()
144 		adev->gmc.ecc_irq.num_types = 1;  in gmc_v11_0_set_irq_funcs()
145 		adev->gmc.ecc_irq.funcs = &gmc_v11_0_ecc_funcs;  in gmc_v11_0_set_irq_funcs()
194 	spin_lock(&adev->gmc.invalidate_lock);  in gmc_v11_0_flush_vm_hub()
252 	spin_unlock(&adev->gmc.invalidate_lock);  in gmc_v11_0_flush_vm_hub()
483 			adev->gmc.vram_start;  in gmc_v11_0_get_vm_pde()
486 	if (!adev->gmc.translate_further)  in gmc_v11_0_get_vm_pde()
542 	adev->gmc.gmc_funcs = &gmc_v11_0_gmc_funcs;  in gmc_v11_0_set_gmc_funcs()
551 		adev->umc.node_inst_num = adev->gmc.num_umc;  in gmc_v11_0_set_umc_funcs()
619 	adev->gmc.shared_aperture_start = 0x2000000000000000ULL;  in gmc_v11_0_early_init()
620 	adev->gmc.shared_aperture_end =  in gmc_v11_0_early_init()
621 		adev->gmc.shared_aperture_start + (4ULL << 30) - 1;  in gmc_v11_0_early_init()
622 	adev->gmc.private_aperture_start = 0x1000000000000000ULL;  in gmc_v11_0_early_init()
623 	adev->gmc.private_aperture_end =  in gmc_v11_0_early_init()
624 		adev->gmc.private_aperture_start + (4ULL << 30) - 1;  in gmc_v11_0_early_init()
642 	return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0);  in gmc_v11_0_late_init()
652 	amdgpu_gmc_vram_location(adev, &adev->gmc, base);  in gmc_v11_0_vram_gtt_location()
676 	adev->gmc.mc_vram_size =  in gmc_v11_0_mc_init()
678 	adev->gmc.real_vram_size = adev->gmc.mc_vram_size;  in gmc_v11_0_mc_init()
685 	adev->gmc.aper_base = pci_resource_start(adev->pdev, 0);  in gmc_v11_0_mc_init()
686 	adev->gmc.aper_size = pci_resource_len(adev->pdev, 0);  in gmc_v11_0_mc_init()
690 		adev->gmc.aper_base = adev->mmhub.funcs->get_mc_fb_offset(adev);  in gmc_v11_0_mc_init()
691 		adev->gmc.aper_size = adev->gmc.real_vram_size;  in gmc_v11_0_mc_init()
695 	adev->gmc.visible_vram_size = adev->gmc.aper_size;  in gmc_v11_0_mc_init()
696 	if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size)  in gmc_v11_0_mc_init()
697 		adev->gmc.visible_vram_size = adev->gmc.real_vram_size;  in gmc_v11_0_mc_init()
701 		adev->gmc.gart_size = 512ULL << 20;  in gmc_v11_0_mc_init()
703 		adev->gmc.gart_size = (u64)amdgpu_gart_size << 20;  in gmc_v11_0_mc_init()
705 	gmc_v11_0_vram_gtt_location(adev, &adev->gmc);  in gmc_v11_0_mc_init()
738 	spin_lock_init(&adev->gmc.invalidate_lock);  in gmc_v11_0_sw_init()
742 	adev->gmc.vram_width = vram_width;  in gmc_v11_0_sw_init()
744 	adev->gmc.vram_type = vram_type;  in gmc_v11_0_sw_init()
745 	adev->gmc.vram_vendor = vram_vendor;  in gmc_v11_0_sw_init()
767 			      &adev->gmc.vm_fault);  in gmc_v11_0_sw_init()
774 			      &adev->gmc.vm_fault);  in gmc_v11_0_sw_init()
781 				      &adev->gmc.ecc_irq);  in gmc_v11_0_sw_init()
790 	adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */  in gmc_v11_0_sw_init()
887 		 (unsigned)(adev->gmc.gart_size >> 20),  in gmc_v11_0_gart_enable()
933 	amdgpu_irq_put(adev, &adev->gmc.ecc_irq, 0);  in gmc_v11_0_hw_fini()
934 	amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0);  in gmc_v11_0_hw_fini()