676 		adev->umc.max_ras_err_cnt_per_query = UMC_V8_7_TOTAL_CHANNEL_NUM;  in gmc_v10_0_set_umc_funcs()
677 		adev->umc.channel_inst_num = UMC_V8_7_CHANNEL_INSTANCE_NUM;  in gmc_v10_0_set_umc_funcs()
678 		adev->umc.umc_inst_num = UMC_V8_7_UMC_INSTANCE_NUM;  in gmc_v10_0_set_umc_funcs()
679 		adev->umc.channel_offs = UMC_V8_7_PER_CHANNEL_OFFSET_SIENNA;  in gmc_v10_0_set_umc_funcs()
680 		adev->umc.channel_idx_tbl = &umc_v8_7_channel_idx_tbl[0][0];  in gmc_v10_0_set_umc_funcs()
681 		adev->umc.ras = &umc_v8_7_ras;  in gmc_v10_0_set_umc_funcs()
686 	if (adev->umc.ras) {  in gmc_v10_0_set_umc_funcs()
687 		amdgpu_ras_register_ras_block(adev, &adev->umc.ras->ras_block);  in gmc_v10_0_set_umc_funcs()
689 		strcpy(adev->umc.ras->ras_block.ras_comm.name, "umc");  in gmc_v10_0_set_umc_funcs()
690 		adev->umc.ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__UMC;  in gmc_v10_0_set_umc_funcs()
691 		adev->umc.ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;  in gmc_v10_0_set_umc_funcs()
692 		adev->umc.ras_if = &adev->umc.ras->ras_block.ras_comm;  in gmc_v10_0_set_umc_funcs()
695 		if (!adev->umc.ras->ras_block.ras_late_init)  in gmc_v10_0_set_umc_funcs()
696 				adev->umc.ras->ras_block.ras_late_init = amdgpu_umc_ras_late_init;  in gmc_v10_0_set_umc_funcs()
699 		if (!adev->umc.ras->ras_block.ras_cb)  in gmc_v10_0_set_umc_funcs()
700 			adev->umc.ras->ras_block.ras_cb = amdgpu_umc_process_ras_data_cb;  in gmc_v10_0_set_umc_funcs()
1114 	if (adev->umc.funcs && adev->umc.funcs->init_registers)  in gmc_v10_0_hw_init()
1115 		adev->umc.funcs->init_registers(adev);  in gmc_v10_0_hw_init()