184 	adev->gmc.vm_fault.num_types = 1;  in gmc_v10_0_set_irq_funcs()
185 	adev->gmc.vm_fault.funcs = &gmc_v10_0_irq_funcs;  in gmc_v10_0_set_irq_funcs()
188 		adev->gmc.ecc_irq.num_types = 1;  in gmc_v10_0_set_irq_funcs()
189 		adev->gmc.ecc_irq.funcs = &gmc_v10_0_ecc_funcs;  in gmc_v10_0_set_irq_funcs()
243 	spin_lock(&adev->gmc.invalidate_lock);  in gmc_v10_0_flush_vm_hub()
301 	spin_unlock(&adev->gmc.invalidate_lock);  in gmc_v10_0_flush_vm_hub()
595 	if (!adev->gmc.translate_further)  in gmc_v10_0_get_vm_pde()
668 	if (adev->gmc.gmc_funcs == NULL)  in gmc_v10_0_set_gmc_funcs()
669 		adev->gmc.gmc_funcs = &gmc_v10_0_gmc_funcs;  in gmc_v10_0_set_gmc_funcs()
750 	adev->gmc.shared_aperture_start = 0x2000000000000000ULL;  in gmc_v10_0_early_init()
751 	adev->gmc.shared_aperture_end =  in gmc_v10_0_early_init()
752 		adev->gmc.shared_aperture_start + (4ULL << 30) - 1;  in gmc_v10_0_early_init()
753 	adev->gmc.private_aperture_start = 0x1000000000000000ULL;  in gmc_v10_0_early_init()
754 	adev->gmc.private_aperture_end =  in gmc_v10_0_early_init()
755 		adev->gmc.private_aperture_start + (4ULL << 30) - 1;  in gmc_v10_0_early_init()
777 	return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0);  in gmc_v10_0_late_init()
788 	base += adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size;  in gmc_v10_0_vram_gtt_location()
790 	amdgpu_gmc_vram_location(adev, &adev->gmc, base);  in gmc_v10_0_vram_gtt_location()
799 		adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size;  in gmc_v10_0_vram_gtt_location()
816 	adev->gmc.mc_vram_size =  in gmc_v10_0_mc_init()
818 	adev->gmc.real_vram_size = adev->gmc.mc_vram_size;  in gmc_v10_0_mc_init()
825 	adev->gmc.aper_base = pci_resource_start(adev->pdev, 0);  in gmc_v10_0_mc_init()
826 	adev->gmc.aper_size = pci_resource_len(adev->pdev, 0);  in gmc_v10_0_mc_init()
830 		adev->gmc.aper_base = adev->gfxhub.funcs->get_mc_fb_offset(adev);  in gmc_v10_0_mc_init()
831 		adev->gmc.aper_size = adev->gmc.real_vram_size;  in gmc_v10_0_mc_init()
836 	adev->gmc.visible_vram_size = adev->gmc.aper_size;  in gmc_v10_0_mc_init()
837 	if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size)  in gmc_v10_0_mc_init()
838 		adev->gmc.visible_vram_size = adev->gmc.real_vram_size;  in gmc_v10_0_mc_init()
844 			adev->gmc.gart_size = 512ULL << 20;  in gmc_v10_0_mc_init()
850 			adev->gmc.gart_size = 1024ULL << 20;  in gmc_v10_0_mc_init()
854 		adev->gmc.gart_size = (u64)amdgpu_gart_size << 20;  in gmc_v10_0_mc_init()
857 	gmc_v10_0_vram_gtt_location(adev, &adev->gmc);  in gmc_v10_0_mc_init()
892 	spin_lock_init(&adev->gmc.invalidate_lock);  in gmc_v10_0_sw_init()
895 		adev->gmc.vram_type = AMDGPU_VRAM_TYPE_DDR4;  in gmc_v10_0_sw_init()
896 		adev->gmc.vram_width = 64;  in gmc_v10_0_sw_init()
898 		adev->gmc.vram_type = AMDGPU_VRAM_TYPE_GDDR6;  in gmc_v10_0_sw_init()
899 		adev->gmc.vram_width = 1 * 128; /* numchan * chansize */  in gmc_v10_0_sw_init()
903 		adev->gmc.vram_width = vram_width;  in gmc_v10_0_sw_init()
905 		adev->gmc.vram_type = vram_type;  in gmc_v10_0_sw_init()
906 		adev->gmc.vram_vendor = vram_vendor;  in gmc_v10_0_sw_init()
911 		adev->gmc.mall_size = 128 * 1024 * 1024;  in gmc_v10_0_sw_init()
914 		adev->gmc.mall_size = 96 * 1024 * 1024;  in gmc_v10_0_sw_init()
917 		adev->gmc.mall_size = 32 * 1024 * 1024;  in gmc_v10_0_sw_init()
920 		adev->gmc.mall_size = 16 * 1024 * 1024;  in gmc_v10_0_sw_init()
923 		adev->gmc.mall_size = 0;  in gmc_v10_0_sw_init()
956 			      &adev->gmc.vm_fault);  in gmc_v10_0_sw_init()
963 			      &adev->gmc.vm_fault);  in gmc_v10_0_sw_init()
970 				      &adev->gmc.ecc_irq);  in gmc_v10_0_sw_init()
979 	adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */  in gmc_v10_0_sw_init()
1083 		 (unsigned)(adev->gmc.gart_size >> 20),  in gmc_v10_0_gart_enable()
1145 	amdgpu_irq_put(adev, &adev->gmc.ecc_irq, 0);  in gmc_v10_0_hw_fini()
1146 	amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0);  in gmc_v10_0_hw_fini()