63 static int gmc_v10_0_ecc_interrupt_state(struct amdgpu_device *adev,  in gmc_v10_0_ecc_interrupt_state()  argument
72 gmc_v10_0_vm_fault_interrupt_state(struct amdgpu_device *adev,  in gmc_v10_0_vm_fault_interrupt_state()  argument
79 		amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB_0, false);  in gmc_v10_0_vm_fault_interrupt_state()
81 		amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB_0, false);  in gmc_v10_0_vm_fault_interrupt_state()
85 		amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB_0, true);  in gmc_v10_0_vm_fault_interrupt_state()
87 		amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB_0, true);  in gmc_v10_0_vm_fault_interrupt_state()
96 static int gmc_v10_0_process_interrupt(struct amdgpu_device *adev,  in gmc_v10_0_process_interrupt()  argument
102 	struct amdgpu_vmhub *hub = &adev->vmhub[entry->vmid_src];  in gmc_v10_0_process_interrupt()
114 		if (entry->ih != &adev->irq.ih_soft &&  in gmc_v10_0_process_interrupt()
115 		    amdgpu_gmc_filter_faults(adev, entry->ih, addr, entry->pasid,  in gmc_v10_0_process_interrupt()
122 		if (entry->ih == &adev->irq.ih) {  in gmc_v10_0_process_interrupt()
123 			amdgpu_irq_delegate(adev, entry, 8);  in gmc_v10_0_process_interrupt()
130 		if (amdgpu_vm_handle_fault(adev, entry->pasid, addr, write_fault))  in gmc_v10_0_process_interrupt()
134 	if (!amdgpu_sriov_vf(adev)) {  in gmc_v10_0_process_interrupt()
141 		    (adev->ip_versions[GC_HWIP][0] < IP_VERSION(10, 3, 0)))  in gmc_v10_0_process_interrupt()
152 	amdgpu_vm_get_task_info(adev, entry->pasid, &task_info);  in gmc_v10_0_process_interrupt()
154 	dev_err(adev->dev,  in gmc_v10_0_process_interrupt()
161 	dev_err(adev->dev, "  in page starting at address 0x%016llx from client 0x%x (%s)\n",  in gmc_v10_0_process_interrupt()
165 	if (!amdgpu_sriov_vf(adev))  in gmc_v10_0_process_interrupt()
166 		hub->vmhub_funcs->print_l2_protection_fault_status(adev,  in gmc_v10_0_process_interrupt()
182 static void gmc_v10_0_set_irq_funcs(struct amdgpu_device *adev)  in gmc_v10_0_set_irq_funcs()  argument
184 	adev->gmc.vm_fault.num_types = 1;  in gmc_v10_0_set_irq_funcs()
185 	adev->gmc.vm_fault.funcs = &gmc_v10_0_irq_funcs;  in gmc_v10_0_set_irq_funcs()
187 	if (!amdgpu_sriov_vf(adev)) {  in gmc_v10_0_set_irq_funcs()
188 		adev->gmc.ecc_irq.num_types = 1;  in gmc_v10_0_set_irq_funcs()
189 		adev->gmc.ecc_irq.funcs = &gmc_v10_0_ecc_funcs;  in gmc_v10_0_set_irq_funcs()
200 static bool gmc_v10_0_use_invalidate_semaphore(struct amdgpu_device *adev,  in gmc_v10_0_use_invalidate_semaphore()  argument
205 		(!amdgpu_sriov_vf(adev)));  in gmc_v10_0_use_invalidate_semaphore()
209 					struct amdgpu_device *adev,  in gmc_v10_0_get_atc_vmid_pasid_mapping_info()  argument
228 static void gmc_v10_0_flush_vm_hub(struct amdgpu_device *adev, uint32_t vmid,  in gmc_v10_0_flush_vm_hub()  argument
231 	bool use_semaphore = gmc_v10_0_use_invalidate_semaphore(adev, vmhub);  in gmc_v10_0_flush_vm_hub()
232 	struct amdgpu_vmhub *hub = &adev->vmhub[vmhub];  in gmc_v10_0_flush_vm_hub()
243 	spin_lock(&adev->gmc.invalidate_lock);  in gmc_v10_0_flush_vm_hub()
253 		for (i = 0; i < adev->usec_timeout; i++) {  in gmc_v10_0_flush_vm_hub()
263 		if (i >= adev->usec_timeout)  in gmc_v10_0_flush_vm_hub()
276 	    (adev->ip_versions[GC_HWIP][0] < IP_VERSION(10, 3, 0)))  in gmc_v10_0_flush_vm_hub()
281 	for (i = 0; i < adev->usec_timeout; i++) {  in gmc_v10_0_flush_vm_hub()
301 	spin_unlock(&adev->gmc.invalidate_lock);  in gmc_v10_0_flush_vm_hub()
303 	if (i < adev->usec_timeout)  in gmc_v10_0_flush_vm_hub()
319 static void gmc_v10_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,  in gmc_v10_0_flush_gpu_tlb()  argument
322 	struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;  in gmc_v10_0_flush_gpu_tlb()
329 	adev->hdp.funcs->flush_hdp(adev, NULL);  in gmc_v10_0_flush_gpu_tlb()
334 	if (adev->gfx.kiq.ring.sched.ready && !adev->enable_mes &&  in gmc_v10_0_flush_gpu_tlb()
335 	    (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev)) &&  in gmc_v10_0_flush_gpu_tlb()
336 	    down_read_trylock(&adev->reset_domain->sem)) {  in gmc_v10_0_flush_gpu_tlb()
337 		struct amdgpu_vmhub *hub = &adev->vmhub[vmhub];  in gmc_v10_0_flush_gpu_tlb()
343 		amdgpu_virt_kiq_reg_write_reg_wait(adev, req, ack, inv_req,  in gmc_v10_0_flush_gpu_tlb()
346 		up_read(&adev->reset_domain->sem);  in gmc_v10_0_flush_gpu_tlb()
350 	mutex_lock(&adev->mman.gtt_window_lock);  in gmc_v10_0_flush_gpu_tlb()
353 		gmc_v10_0_flush_vm_hub(adev, vmid, AMDGPU_MMHUB_0, 0);  in gmc_v10_0_flush_gpu_tlb()
354 		mutex_unlock(&adev->mman.gtt_window_lock);  in gmc_v10_0_flush_gpu_tlb()
360 	if (!adev->mman.buffer_funcs_enabled ||  in gmc_v10_0_flush_gpu_tlb()
361 	    !adev->ib_pool_ready ||  in gmc_v10_0_flush_gpu_tlb()
362 	    amdgpu_in_reset(adev) ||  in gmc_v10_0_flush_gpu_tlb()
364 		gmc_v10_0_flush_vm_hub(adev, vmid, AMDGPU_GFXHUB_0, 0);  in gmc_v10_0_flush_gpu_tlb()
365 		mutex_unlock(&adev->mman.gtt_window_lock);  in gmc_v10_0_flush_gpu_tlb()
374 	r = amdgpu_job_alloc_with_ib(adev, 16 * 4, AMDGPU_IB_POOL_IMMEDIATE,  in gmc_v10_0_flush_gpu_tlb()
379 	job->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gart.bo);  in gmc_v10_0_flush_gpu_tlb()
383 	r = amdgpu_job_submit(job, &adev->mman.entity,  in gmc_v10_0_flush_gpu_tlb()
388 	mutex_unlock(&adev->mman.gtt_window_lock);  in gmc_v10_0_flush_gpu_tlb()
399 	mutex_unlock(&adev->mman.gtt_window_lock);  in gmc_v10_0_flush_gpu_tlb()
413 static int gmc_v10_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev,  in gmc_v10_0_flush_gpu_tlb_pasid()  argument
422 	u32 usec_timeout = amdgpu_sriov_vf(adev) ? SRIOV_USEC_TIMEOUT : adev->usec_timeout;  in gmc_v10_0_flush_gpu_tlb_pasid()
423 	struct amdgpu_ring *ring = &adev->gfx.kiq.ring;  in gmc_v10_0_flush_gpu_tlb_pasid()
424 	struct amdgpu_kiq *kiq = &adev->gfx.kiq;  in gmc_v10_0_flush_gpu_tlb_pasid()
427 		spin_lock(&adev->gfx.kiq.ring_lock);  in gmc_v10_0_flush_gpu_tlb_pasid()
435 			spin_unlock(&adev->gfx.kiq.ring_lock);  in gmc_v10_0_flush_gpu_tlb_pasid()
440 		spin_unlock(&adev->gfx.kiq.ring_lock);  in gmc_v10_0_flush_gpu_tlb_pasid()
443 			dev_err(adev->dev, "wait for kiq fence error: %ld.\n", r);  in gmc_v10_0_flush_gpu_tlb_pasid()
452 		ret = gmc_v10_0_get_atc_vmid_pasid_mapping_info(adev, vmid,  in gmc_v10_0_flush_gpu_tlb_pasid()
456 				for (i = 0; i < adev->num_vmhubs; i++)  in gmc_v10_0_flush_gpu_tlb_pasid()
457 					gmc_v10_0_flush_gpu_tlb(adev, vmid,  in gmc_v10_0_flush_gpu_tlb_pasid()
460 				gmc_v10_0_flush_gpu_tlb(adev, vmid,  in gmc_v10_0_flush_gpu_tlb_pasid()
463 			if (!adev->enable_mes)  in gmc_v10_0_flush_gpu_tlb_pasid()
474 	bool use_semaphore = gmc_v10_0_use_invalidate_semaphore(ring->adev, ring->funcs->vmhub);  in gmc_v10_0_emit_flush_gpu_tlb()
475 	struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];  in gmc_v10_0_emit_flush_gpu_tlb()
522 	struct amdgpu_device *adev = ring->adev;  in gmc_v10_0_emit_pasid_mapping()  local
570 static uint64_t gmc_v10_0_map_mtype(struct amdgpu_device *adev, uint32_t flags)  in gmc_v10_0_map_mtype()  argument
588 static void gmc_v10_0_get_vm_pde(struct amdgpu_device *adev, int level,  in gmc_v10_0_get_vm_pde()  argument
592 		*addr = amdgpu_gmc_vram_mc2pa(adev, *addr);  in gmc_v10_0_get_vm_pde()
595 	if (!adev->gmc.translate_further)  in gmc_v10_0_get_vm_pde()
611 static void gmc_v10_0_get_vm_pte(struct amdgpu_device *adev,  in gmc_v10_0_get_vm_pte()  argument
633 static unsigned gmc_v10_0_get_vbios_fb_size(struct amdgpu_device *adev)  in gmc_v10_0_get_vbios_fb_size()  argument
666 static void gmc_v10_0_set_gmc_funcs(struct amdgpu_device *adev)  in gmc_v10_0_set_gmc_funcs()  argument
668 	if (adev->gmc.gmc_funcs == NULL)  in gmc_v10_0_set_gmc_funcs()
669 		adev->gmc.gmc_funcs = &gmc_v10_0_gmc_funcs;  in gmc_v10_0_set_gmc_funcs()
672 static void gmc_v10_0_set_umc_funcs(struct amdgpu_device *adev)  in gmc_v10_0_set_umc_funcs()  argument
674 	switch (adev->ip_versions[UMC_HWIP][0]) {  in gmc_v10_0_set_umc_funcs()
676 		adev->umc.max_ras_err_cnt_per_query = UMC_V8_7_TOTAL_CHANNEL_NUM;  in gmc_v10_0_set_umc_funcs()
677 		adev->umc.channel_inst_num = UMC_V8_7_CHANNEL_INSTANCE_NUM;  in gmc_v10_0_set_umc_funcs()
678 		adev->umc.umc_inst_num = UMC_V8_7_UMC_INSTANCE_NUM;  in gmc_v10_0_set_umc_funcs()
679 		adev->umc.channel_offs = UMC_V8_7_PER_CHANNEL_OFFSET_SIENNA;  in gmc_v10_0_set_umc_funcs()
680 		adev->umc.channel_idx_tbl = &umc_v8_7_channel_idx_tbl[0][0];  in gmc_v10_0_set_umc_funcs()
681 		adev->umc.ras = &umc_v8_7_ras;  in gmc_v10_0_set_umc_funcs()
686 	if (adev->umc.ras) {  in gmc_v10_0_set_umc_funcs()
687 		amdgpu_ras_register_ras_block(adev, &adev->umc.ras->ras_block);  in gmc_v10_0_set_umc_funcs()
689 		strcpy(adev->umc.ras->ras_block.ras_comm.name, "umc");  in gmc_v10_0_set_umc_funcs()
690 		adev->umc.ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__UMC;  in gmc_v10_0_set_umc_funcs()
691 		adev->umc.ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;  in gmc_v10_0_set_umc_funcs()
692 		adev->umc.ras_if = &adev->umc.ras->ras_block.ras_comm;  in gmc_v10_0_set_umc_funcs()
695 		if (!adev->umc.ras->ras_block.ras_late_init)  in gmc_v10_0_set_umc_funcs()
696 				adev->umc.ras->ras_block.ras_late_init = amdgpu_umc_ras_late_init;  in gmc_v10_0_set_umc_funcs()
699 		if (!adev->umc.ras->ras_block.ras_cb)  in gmc_v10_0_set_umc_funcs()
700 			adev->umc.ras->ras_block.ras_cb = amdgpu_umc_process_ras_data_cb;  in gmc_v10_0_set_umc_funcs()
705 static void gmc_v10_0_set_mmhub_funcs(struct amdgpu_device *adev)  in gmc_v10_0_set_mmhub_funcs()  argument
707 	switch (adev->ip_versions[MMHUB_HWIP][0]) {  in gmc_v10_0_set_mmhub_funcs()
711 		adev->mmhub.funcs = &mmhub_v2_3_funcs;  in gmc_v10_0_set_mmhub_funcs()
714 		adev->mmhub.funcs = &mmhub_v2_0_funcs;  in gmc_v10_0_set_mmhub_funcs()
719 static void gmc_v10_0_set_gfxhub_funcs(struct amdgpu_device *adev)  in gmc_v10_0_set_gfxhub_funcs()  argument
721 	switch (adev->ip_versions[GC_HWIP][0]) {  in gmc_v10_0_set_gfxhub_funcs()
730 		adev->gfxhub.funcs = &gfxhub_v2_1_funcs;  in gmc_v10_0_set_gfxhub_funcs()
733 		adev->gfxhub.funcs = &gfxhub_v2_0_funcs;  in gmc_v10_0_set_gfxhub_funcs()
742 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;  in gmc_v10_0_early_init()  local
744 	gmc_v10_0_set_mmhub_funcs(adev);  in gmc_v10_0_early_init()
745 	gmc_v10_0_set_gfxhub_funcs(adev);  in gmc_v10_0_early_init()
746 	gmc_v10_0_set_gmc_funcs(adev);  in gmc_v10_0_early_init()
747 	gmc_v10_0_set_irq_funcs(adev);  in gmc_v10_0_early_init()
748 	gmc_v10_0_set_umc_funcs(adev);  in gmc_v10_0_early_init()
750 	adev->gmc.shared_aperture_start = 0x2000000000000000ULL;  in gmc_v10_0_early_init()
751 	adev->gmc.shared_aperture_end =  in gmc_v10_0_early_init()
752 		adev->gmc.shared_aperture_start + (4ULL << 30) - 1;  in gmc_v10_0_early_init()
753 	adev->gmc.private_aperture_start = 0x1000000000000000ULL;  in gmc_v10_0_early_init()
754 	adev->gmc.private_aperture_end =  in gmc_v10_0_early_init()
755 		adev->gmc.private_aperture_start + (4ULL << 30) - 1;  in gmc_v10_0_early_init()
757 	r = amdgpu_gmc_ras_early_init(adev);  in gmc_v10_0_early_init()
766 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;  in gmc_v10_0_late_init()  local
769 	r = amdgpu_gmc_allocate_vm_inv_eng(adev);  in gmc_v10_0_late_init()
773 	r = amdgpu_gmc_ras_late_init(adev);  in gmc_v10_0_late_init()
777 	return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0);  in gmc_v10_0_late_init()
780 static void gmc_v10_0_vram_gtt_location(struct amdgpu_device *adev,  in gmc_v10_0_vram_gtt_location()  argument
785 	base = adev->gfxhub.funcs->get_fb_location(adev);  in gmc_v10_0_vram_gtt_location()
788 	base += adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size;  in gmc_v10_0_vram_gtt_location()
790 	amdgpu_gmc_vram_location(adev, &adev->gmc, base);  in gmc_v10_0_vram_gtt_location()
791 	amdgpu_gmc_gart_location(adev, mc);  in gmc_v10_0_vram_gtt_location()
792 	amdgpu_gmc_agp_location(adev, mc);  in gmc_v10_0_vram_gtt_location()
795 	adev->vm_manager.vram_base_offset = adev->gfxhub.funcs->get_mc_fb_offset(adev);  in gmc_v10_0_vram_gtt_location()
798 	adev->vm_manager.vram_base_offset +=  in gmc_v10_0_vram_gtt_location()
799 		adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size;  in gmc_v10_0_vram_gtt_location()
811 static int gmc_v10_0_mc_init(struct amdgpu_device *adev)  in gmc_v10_0_mc_init()  argument
816 	adev->gmc.mc_vram_size =  in gmc_v10_0_mc_init()
817 		adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL;  in gmc_v10_0_mc_init()
818 	adev->gmc.real_vram_size = adev->gmc.mc_vram_size;  in gmc_v10_0_mc_init()
820 	if (!(adev->flags & AMD_IS_APU)) {  in gmc_v10_0_mc_init()
821 		r = amdgpu_device_resize_fb_bar(adev);  in gmc_v10_0_mc_init()
825 	adev->gmc.aper_base = pci_resource_start(adev->pdev, 0);  in gmc_v10_0_mc_init()
826 	adev->gmc.aper_size = pci_resource_len(adev->pdev, 0);  in gmc_v10_0_mc_init()
829 	if ((adev->flags & AMD_IS_APU) && !amdgpu_passthrough(adev)) {  in gmc_v10_0_mc_init()
830 		adev->gmc.aper_base = adev->gfxhub.funcs->get_mc_fb_offset(adev);  in gmc_v10_0_mc_init()
831 		adev->gmc.aper_size = adev->gmc.real_vram_size;  in gmc_v10_0_mc_init()
836 	adev->gmc.visible_vram_size = adev->gmc.aper_size;  in gmc_v10_0_mc_init()
837 	if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size)  in gmc_v10_0_mc_init()
838 		adev->gmc.visible_vram_size = adev->gmc.real_vram_size;  in gmc_v10_0_mc_init()
842 		switch (adev->ip_versions[GC_HWIP][0]) {  in gmc_v10_0_mc_init()
844 			adev->gmc.gart_size = 512ULL << 20;  in gmc_v10_0_mc_init()
850 			adev->gmc.gart_size = 1024ULL << 20;  in gmc_v10_0_mc_init()
854 		adev->gmc.gart_size = (u64)amdgpu_gart_size << 20;  in gmc_v10_0_mc_init()
857 	gmc_v10_0_vram_gtt_location(adev, &adev->gmc);  in gmc_v10_0_mc_init()
862 static int gmc_v10_0_gart_init(struct amdgpu_device *adev)  in gmc_v10_0_gart_init()  argument
866 	if (adev->gart.bo) {  in gmc_v10_0_gart_init()
872 	r = amdgpu_gart_init(adev);  in gmc_v10_0_gart_init()
876 	adev->gart.table_size = adev->gart.num_gpu_pages * 8;  in gmc_v10_0_gart_init()
877 	adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_NV10(MTYPE_UC) |  in gmc_v10_0_gart_init()
880 	return amdgpu_gart_table_vram_alloc(adev);  in gmc_v10_0_gart_init()
886 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;  in gmc_v10_0_sw_init()  local
888 	adev->gfxhub.funcs->init(adev);  in gmc_v10_0_sw_init()
890 	adev->mmhub.funcs->init(adev);  in gmc_v10_0_sw_init()
892 	spin_lock_init(&adev->gmc.invalidate_lock);  in gmc_v10_0_sw_init()
894 	if ((adev->flags & AMD_IS_APU) && amdgpu_emu_mode == 1) {  in gmc_v10_0_sw_init()
895 		adev->gmc.vram_type = AMDGPU_VRAM_TYPE_DDR4;  in gmc_v10_0_sw_init()
896 		adev->gmc.vram_width = 64;  in gmc_v10_0_sw_init()
898 		adev->gmc.vram_type = AMDGPU_VRAM_TYPE_GDDR6;  in gmc_v10_0_sw_init()
899 		adev->gmc.vram_width = 1 * 128; /* numchan * chansize */  in gmc_v10_0_sw_init()
901 		r = amdgpu_atomfirmware_get_vram_info(adev,  in gmc_v10_0_sw_init()
903 		adev->gmc.vram_width = vram_width;  in gmc_v10_0_sw_init()
905 		adev->gmc.vram_type = vram_type;  in gmc_v10_0_sw_init()
906 		adev->gmc.vram_vendor = vram_vendor;  in gmc_v10_0_sw_init()
909 	switch (adev->ip_versions[GC_HWIP][0]) {  in gmc_v10_0_sw_init()
911 		adev->gmc.mall_size = 128 * 1024 * 1024;  in gmc_v10_0_sw_init()
914 		adev->gmc.mall_size = 96 * 1024 * 1024;  in gmc_v10_0_sw_init()
917 		adev->gmc.mall_size = 32 * 1024 * 1024;  in gmc_v10_0_sw_init()
920 		adev->gmc.mall_size = 16 * 1024 * 1024;  in gmc_v10_0_sw_init()
923 		adev->gmc.mall_size = 0;  in gmc_v10_0_sw_init()
927 	switch (adev->ip_versions[GC_HWIP][0]) {  in gmc_v10_0_sw_init()
941 		adev->num_vmhubs = 2;  in gmc_v10_0_sw_init()
947 		amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);  in gmc_v10_0_sw_init()
954 	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC,  in gmc_v10_0_sw_init()
956 			      &adev->gmc.vm_fault);  in gmc_v10_0_sw_init()
961 	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_UTCL2,  in gmc_v10_0_sw_init()
963 			      &adev->gmc.vm_fault);  in gmc_v10_0_sw_init()
967 	if (!amdgpu_sriov_vf(adev)) {  in gmc_v10_0_sw_init()
969 		r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DF, 0,  in gmc_v10_0_sw_init()
970 				      &adev->gmc.ecc_irq);  in gmc_v10_0_sw_init()
979 	adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */  in gmc_v10_0_sw_init()
981 	r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(44));  in gmc_v10_0_sw_init()
987 	adev->need_swiotlb = drm_need_swiotlb(44);  in gmc_v10_0_sw_init()
989 	r = gmc_v10_0_mc_init(adev);  in gmc_v10_0_sw_init()
993 	amdgpu_gmc_get_vbios_allocations(adev);  in gmc_v10_0_sw_init()
996 	r = amdgpu_bo_init(adev);  in gmc_v10_0_sw_init()
1000 	r = gmc_v10_0_gart_init(adev);  in gmc_v10_0_sw_init()
1010 	adev->vm_manager.first_kfd_vmid = 8;  in gmc_v10_0_sw_init()
1012 	amdgpu_vm_manager_init(adev);  in gmc_v10_0_sw_init()
1024 static void gmc_v10_0_gart_fini(struct amdgpu_device *adev)  in gmc_v10_0_gart_fini()  argument
1026 	amdgpu_gart_table_vram_free(adev);  in gmc_v10_0_gart_fini()
1031 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;  in gmc_v10_0_sw_fini()  local
1033 	amdgpu_vm_manager_fini(adev);  in gmc_v10_0_sw_fini()
1034 	gmc_v10_0_gart_fini(adev);  in gmc_v10_0_sw_fini()
1035 	amdgpu_gem_force_release(adev);  in gmc_v10_0_sw_fini()
1036 	amdgpu_bo_fini(adev);  in gmc_v10_0_sw_fini()
1041 static void gmc_v10_0_init_golden_registers(struct amdgpu_device *adev)  in gmc_v10_0_init_golden_registers()  argument
1050 static int gmc_v10_0_gart_enable(struct amdgpu_device *adev)  in gmc_v10_0_gart_enable()  argument
1055 	if (adev->gart.bo == NULL) {  in gmc_v10_0_gart_enable()
1056 		dev_err(adev->dev, "No VRAM object for PCIE GART.\n");  in gmc_v10_0_gart_enable()
1060 	amdgpu_gtt_mgr_recover(&adev->mman.gtt_mgr);  in gmc_v10_0_gart_enable()
1061 	r = adev->gfxhub.funcs->gart_enable(adev);  in gmc_v10_0_gart_enable()
1065 	r = adev->mmhub.funcs->gart_enable(adev);  in gmc_v10_0_gart_enable()
1069 	adev->hdp.funcs->init_registers(adev);  in gmc_v10_0_gart_enable()
1072 	adev->hdp.funcs->flush_hdp(adev, NULL);  in gmc_v10_0_gart_enable()
1077 	adev->gfxhub.funcs->set_fault_enable_default(adev, value);  in gmc_v10_0_gart_enable()
1078 	adev->mmhub.funcs->set_fault_enable_default(adev, value);  in gmc_v10_0_gart_enable()
1079 	gmc_v10_0_flush_gpu_tlb(adev, 0, AMDGPU_MMHUB_0, 0);  in gmc_v10_0_gart_enable()
1080 	gmc_v10_0_flush_gpu_tlb(adev, 0, AMDGPU_GFXHUB_0, 0);  in gmc_v10_0_gart_enable()
1083 		 (unsigned)(adev->gmc.gart_size >> 20),  in gmc_v10_0_gart_enable()
1084 		 (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo));  in gmc_v10_0_gart_enable()
1092 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;  in gmc_v10_0_hw_init()  local
1095 	gmc_v10_0_init_golden_registers(adev);  in gmc_v10_0_hw_init()
1101 	if (adev->gfxhub.funcs && adev->gfxhub.funcs->utcl2_harvest)  in gmc_v10_0_hw_init()
1102 		adev->gfxhub.funcs->utcl2_harvest(adev);  in gmc_v10_0_hw_init()
1104 	r = gmc_v10_0_gart_enable(adev);  in gmc_v10_0_hw_init()
1109 		r = amdgpu_gmc_vram_checking(adev);  in gmc_v10_0_hw_init()
1114 	if (adev->umc.funcs && adev->umc.funcs->init_registers)  in gmc_v10_0_hw_init()
1115 		adev->umc.funcs->init_registers(adev);  in gmc_v10_0_hw_init()
1127 static void gmc_v10_0_gart_disable(struct amdgpu_device *adev)  in gmc_v10_0_gart_disable()  argument
1129 	adev->gfxhub.funcs->gart_disable(adev);  in gmc_v10_0_gart_disable()
1130 	adev->mmhub.funcs->gart_disable(adev);  in gmc_v10_0_gart_disable()
1135 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;  in gmc_v10_0_hw_fini()  local
1137 	gmc_v10_0_gart_disable(adev);  in gmc_v10_0_hw_fini()
1139 	if (amdgpu_sriov_vf(adev)) {  in gmc_v10_0_hw_fini()
1145 	amdgpu_irq_put(adev, &adev->gmc.ecc_irq, 0);  in gmc_v10_0_hw_fini()
1146 	amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0);  in gmc_v10_0_hw_fini()
1153 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;  in gmc_v10_0_suspend()  local
1155 	gmc_v10_0_hw_fini(adev);  in gmc_v10_0_suspend()
1163 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;  in gmc_v10_0_resume()  local
1165 	r = gmc_v10_0_hw_init(adev);  in gmc_v10_0_resume()
1169 	amdgpu_vmid_reset_all(adev);  in gmc_v10_0_resume()
1195 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;  in gmc_v10_0_set_clockgating_state()  local
1202 	if (adev->in_s0ix && adev->ip_versions[DF_HWIP][0] > IP_VERSION(3, 0, 2)) {  in gmc_v10_0_set_clockgating_state()
1203 		dev_dbg(adev->dev, "keep mmhub clock gating being enabled for s0ix\n");  in gmc_v10_0_set_clockgating_state()
1207 	r = adev->mmhub.funcs->set_clockgating(adev, state);  in gmc_v10_0_set_clockgating_state()
1211 	if (adev->ip_versions[ATHUB_HWIP][0] >= IP_VERSION(2, 1, 0))  in gmc_v10_0_set_clockgating_state()
1212 		return athub_v2_1_set_clockgating(adev, state);  in gmc_v10_0_set_clockgating_state()
1214 		return athub_v2_0_set_clockgating(adev, state);  in gmc_v10_0_set_clockgating_state()
1219 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;  in gmc_v10_0_get_clockgating_state()  local
1221 	if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 3) ||  in gmc_v10_0_get_clockgating_state()
1222 	    adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 4))  in gmc_v10_0_get_clockgating_state()
1225 	adev->mmhub.funcs->get_clockgating(adev, flags);  in gmc_v10_0_get_clockgating_state()
1227 	if (adev->ip_versions[ATHUB_HWIP][0] >= IP_VERSION(2, 1, 0))  in gmc_v10_0_get_clockgating_state()
1228 		athub_v2_1_get_clockgating(adev, flags);  in gmc_v10_0_get_clockgating_state()
1230 		athub_v2_0_get_clockgating(adev, flags);  in gmc_v10_0_get_clockgating_state()