850 	amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));  in gfx_v8_0_ring_test_ring()
891 	ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3);  in gfx_v8_0_ring_test_ib()
1250 	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));  in gfx_v8_0_get_csb_buffer()
1253 	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));  in gfx_v8_0_get_csb_buffer()
1261 					cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));  in gfx_v8_0_get_csb_buffer()
1272 	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 2));  in gfx_v8_0_get_csb_buffer()
1278 	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));  in gfx_v8_0_get_csb_buffer()
1281 	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));  in gfx_v8_0_get_csb_buffer()
1570 		ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1);  in gfx_v8_0_do_edc_gpr_workarounds()
1576 	ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2);  in gfx_v8_0_do_edc_gpr_workarounds()
1582 	ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3);  in gfx_v8_0_do_edc_gpr_workarounds()
1590 	ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0);  in gfx_v8_0_do_edc_gpr_workarounds()
1596 		ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1);  in gfx_v8_0_do_edc_gpr_workarounds()
1602 	ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2);  in gfx_v8_0_do_edc_gpr_workarounds()
1608 	ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3);  in gfx_v8_0_do_edc_gpr_workarounds()
1616 	ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0);  in gfx_v8_0_do_edc_gpr_workarounds()
1622 		ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1);  in gfx_v8_0_do_edc_gpr_workarounds()
1628 	ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2);  in gfx_v8_0_do_edc_gpr_workarounds()
1634 	ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3);  in gfx_v8_0_do_edc_gpr_workarounds()
1642 	ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0);  in gfx_v8_0_do_edc_gpr_workarounds()
4186 	amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));  in gfx_v8_0_cp_gfx_start()
4189 	amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));  in gfx_v8_0_cp_gfx_start()
4197 				       PACKET3(PACKET3_SET_CONTEXT_REG,  in gfx_v8_0_cp_gfx_start()
4207 	amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));  in gfx_v8_0_cp_gfx_start()
4212 	amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));  in gfx_v8_0_cp_gfx_start()
4215 	amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));  in gfx_v8_0_cp_gfx_start()
4219 	amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));  in gfx_v8_0_cp_gfx_start()
4369 	amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));  in gfx_v8_0_kiq_kcq_enable()
4383 		amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));  in gfx_v8_0_kiq_kcq_enable()
4845 		amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));  in gfx_v8_0_kcq_disable()
5187 	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));  in gfx_v8_0_ring_emit_gds_switch()
5195 	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));  in gfx_v8_0_ring_emit_gds_switch()
5203 	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));  in gfx_v8_0_ring_emit_gds_switch()
5211 	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));  in gfx_v8_0_ring_emit_gds_switch()
6088 	amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));  in gfx_v8_0_ring_emit_hdp_flush()
6101 	amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));  in gfx_v8_0_ring_emit_vgt_flush()
6105 	amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));  in gfx_v8_0_ring_emit_vgt_flush()
6119 		header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);  in gfx_v8_0_ring_emit_ib_gfx()
6121 		header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);  in gfx_v8_0_ring_emit_ib_gfx()
6161 		amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));  in gfx_v8_0_ring_emit_ib_compute()
6166 	amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));  in gfx_v8_0_ring_emit_ib_compute()
6185 	amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));  in gfx_v8_0_ring_emit_fence_gfx()
6199 	amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));  in gfx_v8_0_ring_emit_fence_gfx()
6219 	amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));  in gfx_v8_0_ring_emit_pipeline_sync()
6238 	amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));  in gfx_v8_0_ring_emit_vm_flush()
6251 		amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));  in gfx_v8_0_ring_emit_vm_flush()
6278 	amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 5));  in gfx_v8_0_ring_emit_fence_compute()
6298 	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));  in gfx_v8_0_ring_emit_fence_kiq()
6307 		amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));  in gfx_v8_0_ring_emit_fence_kiq()
6318 	amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));  in gfx_v8_ring_emit_sb()
6350 	amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));  in gfx_v8_ring_emit_cntxcntl()
6359 	amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3));  in gfx_v8_0_ring_emit_init_cond_exec()
6387 	amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));  in gfx_v8_0_ring_emit_rreg()
6416 	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));  in gfx_v8_0_ring_emit_wreg()
6813 	amdgpu_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));  in gfx_v8_0_emit_mem_sync()
6826 	amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 5));  in gfx_v8_0_emit_mem_sync_compute()
6923 	.nop = PACKET3(PACKET3_NOP, 0x3FFF),
6970 	.nop = PACKET3(PACKET3_NOP, 0x3FFF),
7004 	.nop = PACKET3(PACKET3_NOP, 0x3FFF),
7214 	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt_ce));  in gfx_v8_0_ring_emit_ce_meta()
7247 	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt_de));  in gfx_v8_0_ring_emit_de_meta()