2520 	for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {  in gfx_v7_0_cp_gfx_start()
3271 			adev->gfx.rlc.reg_list = spectre_rlc_save_restore_register_list;  in gfx_v7_0_rlc_init()
3272 			adev->gfx.rlc.reg_list_size =  in gfx_v7_0_rlc_init()
3275 			adev->gfx.rlc.reg_list = kalindi_rlc_save_restore_register_list;  in gfx_v7_0_rlc_init()
3276 			adev->gfx.rlc.reg_list_size =  in gfx_v7_0_rlc_init()
3280 	adev->gfx.rlc.cs_data = ci_cs_data;  in gfx_v7_0_rlc_init()
3281 	adev->gfx.rlc.cp_table_size = ALIGN(CP_ME_TABLE_SIZE * 5 * 4, 2048); /* CP JT */  in gfx_v7_0_rlc_init()
3282 	adev->gfx.rlc.cp_table_size += 64 * 1024; /* GDS */  in gfx_v7_0_rlc_init()
3284 	src_ptr = adev->gfx.rlc.reg_list;  in gfx_v7_0_rlc_init()
3285 	dws = adev->gfx.rlc.reg_list_size;  in gfx_v7_0_rlc_init()
3288 	cs_data = adev->gfx.rlc.cs_data;  in gfx_v7_0_rlc_init()
3304 	if (adev->gfx.rlc.cp_table_size) {  in gfx_v7_0_rlc_init()
3311 	if (adev->gfx.rlc.funcs->update_spm_vmid)  in gfx_v7_0_rlc_init()
3312 		adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf);  in gfx_v7_0_rlc_init()
3359 static void gfx_v7_0_update_rlc(struct amdgpu_device *adev, u32 rlc)  in gfx_v7_0_update_rlc()  argument
3364 	if (tmp != rlc)  in gfx_v7_0_update_rlc()
3365 		WREG32(mmRLC_CNTL, rlc);  in gfx_v7_0_update_rlc()
3496 	adev->gfx.rlc.funcs->stop(adev);  in gfx_v7_0_rlc_resume()
3502 	adev->gfx.rlc.funcs->reset(adev);  in gfx_v7_0_rlc_resume()
3533 	adev->gfx.rlc.funcs->start(adev);  in gfx_v7_0_rlc_resume()
3866 	if (adev->gfx.rlc.cs_data) {  in gfx_v7_0_init_gfx_cgpg()
3868 		WREG32(mmRLC_GPM_SCRATCH_DATA, upper_32_bits(adev->gfx.rlc.clear_state_gpu_addr));  in gfx_v7_0_init_gfx_cgpg()
3869 		WREG32(mmRLC_GPM_SCRATCH_DATA, lower_32_bits(adev->gfx.rlc.clear_state_gpu_addr));  in gfx_v7_0_init_gfx_cgpg()
3870 		WREG32(mmRLC_GPM_SCRATCH_DATA, adev->gfx.rlc.clear_state_size);  in gfx_v7_0_init_gfx_cgpg()
3876 	if (adev->gfx.rlc.reg_list) {  in gfx_v7_0_init_gfx_cgpg()
3878 		for (i = 0; i < adev->gfx.rlc.reg_list_size; i++)  in gfx_v7_0_init_gfx_cgpg()
3879 			WREG32(mmRLC_GPM_SCRATCH_DATA, adev->gfx.rlc.reg_list[i]);  in gfx_v7_0_init_gfx_cgpg()
3887 	WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8);  in gfx_v7_0_init_gfx_cgpg()
3888 	WREG32(mmRLC_JUMP_TABLE_RESTORE, adev->gfx.rlc.cp_table_gpu_addr >> 8);  in gfx_v7_0_init_gfx_cgpg()
3923 	if (adev->gfx.rlc.cs_data == NULL)  in gfx_v7_0_get_csb_size()
3931 	for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {  in gfx_v7_0_get_csb_size()
3956 	if (adev->gfx.rlc.cs_data == NULL)  in gfx_v7_0_get_csb_buffer()
3968 	for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {  in gfx_v7_0_get_csb_buffer()
4218 	adev->gfx.rlc.funcs = &gfx_v7_0_rlc_funcs;  in gfx_v7_0_early_init()
4462 	r = adev->gfx.rlc.funcs->init(adev);  in gfx_v7_0_sw_init()
4526 	amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,  in gfx_v7_0_sw_fini()
4527 				&adev->gfx.rlc.clear_state_gpu_addr,  in gfx_v7_0_sw_fini()
4528 				(void **)&adev->gfx.rlc.cs_ptr);  in gfx_v7_0_sw_fini()
4529 	if (adev->gfx.rlc.cp_table_size) {  in gfx_v7_0_sw_fini()
4530 		amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,  in gfx_v7_0_sw_fini()
4531 				&adev->gfx.rlc.cp_table_gpu_addr,  in gfx_v7_0_sw_fini()
4532 				(void **)&adev->gfx.rlc.cp_table_ptr);  in gfx_v7_0_sw_fini()
4547 	adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr);  in gfx_v7_0_hw_init()
4549 	r = adev->gfx.rlc.funcs->resume(adev);  in gfx_v7_0_hw_init()
4567 	adev->gfx.rlc.funcs->stop(adev);  in gfx_v7_0_hw_fini()
4652 		adev->gfx.rlc.funcs->stop(adev);  in gfx_v7_0_soft_reset()