Lines Matching refs:RREG32
1625 data = RREG32(mmCC_RB_BACKEND_DISABLE); in gfx_v7_0_get_rb_active_bitmap()
1626 data |= RREG32(mmGC_USER_RB_BACKEND_DISABLE); in gfx_v7_0_get_rb_active_bitmap()
1829 RREG32(mmCC_RB_BACKEND_DISABLE); in gfx_v7_0_setup_rb()
1831 RREG32(mmGC_USER_RB_BACKEND_DISABLE); in gfx_v7_0_setup_rb()
1833 RREG32(mmPA_SC_RASTER_CONFIG); in gfx_v7_0_setup_rb()
1835 RREG32(mmPA_SC_RASTER_CONFIG_1); in gfx_v7_0_setup_rb()
1991 tmp = RREG32(mmSPI_CONFIG_CNTL); in gfx_v7_0_constants_init()
1999 tmp = RREG32(mmDB_DEBUG2) & ~0xf00fffff; in gfx_v7_0_constants_init()
2003 tmp = RREG32(mmDB_DEBUG3) & ~0x0002021c; in gfx_v7_0_constants_init()
2007 tmp = RREG32(mmCB_HW_CONTROL) & ~0x00010000; in gfx_v7_0_constants_init()
2040 tmp = RREG32(mmSPI_ARB_PRIORITY); in gfx_v7_0_constants_init()
2080 tmp = RREG32(mmSCRATCH_REG0); in gfx_v7_0_ring_test_ring()
2355 tmp = RREG32(mmSCRATCH_REG0); in gfx_v7_0_ring_test_ib()
2630 return RREG32(mmCP_RB0_WPTR); in gfx_v7_0_ring_get_wptr_gfx()
2638 (void)RREG32(mmCP_RB0_WPTR); in gfx_v7_0_ring_set_wptr_gfx()
2854 tmp = RREG32(mmCP_HPD_EOP_CONTROL); in gfx_v7_0_compute_pipe_init()
2868 if (RREG32(mmCP_HQD_ACTIVE) & 1) { in gfx_v7_0_mqd_deactivate()
2871 if (!(RREG32(mmCP_HQD_ACTIVE) & 1)) in gfx_v7_0_mqd_deactivate()
2906 RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL); in gfx_v7_0_mqd_init()
2917 mqd->cp_mqd_control = RREG32(mmCP_MQD_CONTROL); in gfx_v7_0_mqd_init()
2926 mqd->cp_hqd_pq_control = RREG32(mmCP_HQD_PQ_CONTROL); in gfx_v7_0_mqd_init()
2961 RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL); in gfx_v7_0_mqd_init()
2980 mqd->cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR); in gfx_v7_0_mqd_init()
2986 mqd->cp_hqd_ib_control = RREG32(mmCP_HQD_IB_CONTROL); in gfx_v7_0_mqd_init()
2987 mqd->cp_hqd_ib_base_addr_lo = RREG32(mmCP_HQD_IB_BASE_ADDR); in gfx_v7_0_mqd_init()
2988 mqd->cp_hqd_ib_base_addr_hi = RREG32(mmCP_HQD_IB_BASE_ADDR_HI); in gfx_v7_0_mqd_init()
2989 mqd->cp_hqd_ib_rptr = RREG32(mmCP_HQD_IB_RPTR); in gfx_v7_0_mqd_init()
2990 mqd->cp_hqd_persistent_state = RREG32(mmCP_HQD_PERSISTENT_STATE); in gfx_v7_0_mqd_init()
2991 mqd->cp_hqd_sema_cmd = RREG32(mmCP_HQD_SEMA_CMD); in gfx_v7_0_mqd_init()
2992 mqd->cp_hqd_msg_type = RREG32(mmCP_HQD_MSG_TYPE); in gfx_v7_0_mqd_init()
2993 mqd->cp_hqd_atomic0_preop_lo = RREG32(mmCP_HQD_ATOMIC0_PREOP_LO); in gfx_v7_0_mqd_init()
2994 mqd->cp_hqd_atomic0_preop_hi = RREG32(mmCP_HQD_ATOMIC0_PREOP_HI); in gfx_v7_0_mqd_init()
2995 mqd->cp_hqd_atomic1_preop_lo = RREG32(mmCP_HQD_ATOMIC1_PREOP_LO); in gfx_v7_0_mqd_init()
2996 mqd->cp_hqd_atomic1_preop_hi = RREG32(mmCP_HQD_ATOMIC1_PREOP_HI); in gfx_v7_0_mqd_init()
2997 mqd->cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR); in gfx_v7_0_mqd_init()
2998 mqd->cp_hqd_quantum = RREG32(mmCP_HQD_QUANTUM); in gfx_v7_0_mqd_init()
2999 mqd->cp_hqd_pipe_priority = RREG32(mmCP_HQD_PIPE_PRIORITY); in gfx_v7_0_mqd_init()
3000 mqd->cp_hqd_queue_priority = RREG32(mmCP_HQD_QUEUE_PRIORITY); in gfx_v7_0_mqd_init()
3001 mqd->cp_hqd_iq_rptr = RREG32(mmCP_HQD_IQ_RPTR); in gfx_v7_0_mqd_init()
3017 tmp = RREG32(mmCP_PQ_WPTR_POLL_CNTL); in gfx_v7_0_mqd_commit()
3078 tmp = RREG32(mmCP_CPF_DEBUG); in gfx_v7_0_cp_compute_resume()
3129 u32 tmp = RREG32(mmCP_INT_CNTL_RING0); in gfx_v7_0_enable_gui_idle_interrupt()
3321 tmp = RREG32(mmRLC_LB_CNTL); in gfx_v7_0_enable_lbpw()
3339 if (RREG32(mmRLC_SERDES_CU_MASTER_BUSY) == 0) in gfx_v7_0_wait_for_rlc_serdes()
3353 if ((RREG32(mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0) in gfx_v7_0_wait_for_rlc_serdes()
3363 tmp = RREG32(mmRLC_CNTL); in gfx_v7_0_update_rlc()
3372 orig = data = RREG32(mmRLC_CNTL); in gfx_v7_0_halt_rlc()
3381 if ((RREG32(mmRLC_GPM_STAT) & RLC_GPM_STAT__RLC_BUSY_MASK) == 0) in gfx_v7_0_halt_rlc()
3407 if ((RREG32(mmRLC_GPM_STAT) & mask) == mask) in gfx_v7_0_set_safe_mode()
3413 if ((RREG32(mmRLC_GPR_REG2) & 0x1) == 0) in gfx_v7_0_set_safe_mode()
3461 u32 tmp = RREG32(mmGRBM_SOFT_RESET); in gfx_v7_0_rlc_reset()
3499 tmp = RREG32(mmRLC_CGCG_CGLS_CTRL) & 0xfffffffc; in gfx_v7_0_rlc_resume()
3544 data = RREG32(mmRLC_SPM_VMID); in gfx_v7_0_update_spm_vmid()
3558 orig = data = RREG32(mmRLC_CGCG_CGLS_CTRL); in gfx_v7_0_enable_cgcg()
3584 RREG32(mmCB_CGTT_SCLK_CTRL); in gfx_v7_0_enable_cgcg()
3585 RREG32(mmCB_CGTT_SCLK_CTRL); in gfx_v7_0_enable_cgcg()
3586 RREG32(mmCB_CGTT_SCLK_CTRL); in gfx_v7_0_enable_cgcg()
3587 RREG32(mmCB_CGTT_SCLK_CTRL); in gfx_v7_0_enable_cgcg()
3604 orig = data = RREG32(mmCP_MEM_SLP_CNTL); in gfx_v7_0_enable_mgcg()
3611 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE); in gfx_v7_0_enable_mgcg()
3631 orig = data = RREG32(mmCGTS_SM_CTRL_REG); in gfx_v7_0_enable_mgcg()
3646 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE); in gfx_v7_0_enable_mgcg()
3651 data = RREG32(mmRLC_MEM_SLP_CNTL); in gfx_v7_0_enable_mgcg()
3657 data = RREG32(mmCP_MEM_SLP_CNTL); in gfx_v7_0_enable_mgcg()
3663 orig = data = RREG32(mmCGTS_SM_CTRL_REG); in gfx_v7_0_enable_mgcg()
3702 orig = data = RREG32(mmRLC_PG_CNTL); in gfx_v7_0_enable_sclk_slowdown_on_pu()
3716 orig = data = RREG32(mmRLC_PG_CNTL); in gfx_v7_0_enable_sclk_slowdown_on_pd()
3729 orig = data = RREG32(mmRLC_PG_CNTL); in gfx_v7_0_enable_cp_pg()
3742 orig = data = RREG32(mmRLC_PG_CNTL); in gfx_v7_0_enable_gds_pg()
3765 orig = data = RREG32(mmRLC_PG_CNTL); in gfx_v7_0_enable_gfx_cgpg()
3770 orig = data = RREG32(mmRLC_AUTO_PG_CTRL); in gfx_v7_0_enable_gfx_cgpg()
3775 orig = data = RREG32(mmRLC_PG_CNTL); in gfx_v7_0_enable_gfx_cgpg()
3780 orig = data = RREG32(mmRLC_AUTO_PG_CTRL); in gfx_v7_0_enable_gfx_cgpg()
3785 data = RREG32(mmDB_RENDER_CONTROL); in gfx_v7_0_enable_gfx_cgpg()
3807 data = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG); in gfx_v7_0_get_cu_active_bitmap()
3808 data |= RREG32(mmGC_USER_SHADER_ARRAY_CONFIG); in gfx_v7_0_get_cu_active_bitmap()
3824 tmp = RREG32(mmRLC_MAX_PG_CU); in gfx_v7_0_init_ao_cu_mask()
3835 orig = data = RREG32(mmRLC_PG_CNTL); in gfx_v7_0_enable_gfx_static_mgpg()
3849 orig = data = RREG32(mmRLC_PG_CNTL); in gfx_v7_0_enable_gfx_dynamic_mgpg()
3882 orig = data = RREG32(mmRLC_PG_CNTL); in gfx_v7_0_init_gfx_cgpg()
3890 data = RREG32(mmCP_RB_WPTR_POLL_CNTL); in gfx_v7_0_init_gfx_cgpg()
3898 data = RREG32(mmRLC_PG_DELAY_2); in gfx_v7_0_init_gfx_cgpg()
3903 data = RREG32(mmRLC_AUTO_PG_CTRL); in gfx_v7_0_init_gfx_cgpg()
4065 clock = (uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_LSB) | in gfx_v7_0_get_gpu_clock_counter()
4066 ((uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL); in gfx_v7_0_get_gpu_clock_counter()
4129 return RREG32(mmSQ_IND_DATA); in wave_read_ind()
4144 *(out++) = RREG32(mmSQ_IND_DATA); in wave_read_regs()
4322 adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG); in gfx_v7_0_gpu_early_init()
4334 tmp = RREG32(mmMC_FUS_DRAM0_BANK_ADDR_MAPPING); in gfx_v7_0_gpu_early_init()
4338 tmp = RREG32(mmMC_FUS_DRAM1_BANK_ADDR_MAPPING); in gfx_v7_0_gpu_early_init()
4591 if (RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK) in gfx_v7_0_is_idle()
4605 tmp = RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK; in gfx_v7_0_wait_for_idle()
4621 tmp = RREG32(mmGRBM_STATUS); in gfx_v7_0_soft_reset()
4637 tmp = RREG32(mmGRBM_STATUS2); in gfx_v7_0_soft_reset()
4642 tmp = RREG32(mmSRBM_STATUS); in gfx_v7_0_soft_reset()
4661 tmp = RREG32(mmGRBM_SOFT_RESET); in gfx_v7_0_soft_reset()
4665 tmp = RREG32(mmGRBM_SOFT_RESET); in gfx_v7_0_soft_reset()
4671 tmp = RREG32(mmGRBM_SOFT_RESET); in gfx_v7_0_soft_reset()
4675 tmp = RREG32(mmSRBM_SOFT_RESET); in gfx_v7_0_soft_reset()
4679 tmp = RREG32(mmSRBM_SOFT_RESET); in gfx_v7_0_soft_reset()
4685 tmp = RREG32(mmSRBM_SOFT_RESET); in gfx_v7_0_soft_reset()
4700 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); in gfx_v7_0_set_gfx_eop_interrupt_state()
4705 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); in gfx_v7_0_set_gfx_eop_interrupt_state()
4751 mec_int_cntl = RREG32(mec_int_cntl_reg); in gfx_v7_0_set_compute_eop_interrupt_state()
4756 mec_int_cntl = RREG32(mec_int_cntl_reg); in gfx_v7_0_set_compute_eop_interrupt_state()
4774 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); in gfx_v7_0_set_priv_reg_fault_state()
4779 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); in gfx_v7_0_set_priv_reg_fault_state()
4799 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); in gfx_v7_0_set_priv_inst_fault_state()
4804 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); in gfx_v7_0_set_priv_inst_fault_state()
5120 adev->gds.gds_size = RREG32(mmGDS_VMID0_SIZE); in gfx_v7_0_set_gds_init()
5123 adev->gds.gds_compute_max_wave_id = RREG32(mmGDS_COMPUTE_MAX_WAVE_ID); in gfx_v7_0_set_gds_init()