Lines Matching +full:v1 +full:- +full:v6
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
32 #include "atom-bits.h"
43 struct drm_device *dev = crtc->dev; in amdgpu_atombios_crtc_overscan_setup()
52 args.ucCRTC = amdgpu_crtc->crtc_id; in amdgpu_atombios_crtc_overscan_setup()
54 switch (amdgpu_crtc->rmx_type) { in amdgpu_atombios_crtc_overscan_setup()
56 args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2); in amdgpu_atombios_crtc_overscan_setup()
57 args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2); in amdgpu_atombios_crtc_overscan_setup()
58 args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2); in amdgpu_atombios_crtc_overscan_setup()
59 args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2); in amdgpu_atombios_crtc_overscan_setup()
62 a1 = mode->crtc_vdisplay * adjusted_mode->crtc_hdisplay; in amdgpu_atombios_crtc_overscan_setup()
63 a2 = adjusted_mode->crtc_vdisplay * mode->crtc_hdisplay; in amdgpu_atombios_crtc_overscan_setup()
66 …args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2); in amdgpu_atombios_crtc_overscan_setup()
67 …args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2… in amdgpu_atombios_crtc_overscan_setup()
69 … args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2); in amdgpu_atombios_crtc_overscan_setup()
70 …args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / … in amdgpu_atombios_crtc_overscan_setup()
75 args.usOverscanRight = cpu_to_le16(amdgpu_crtc->h_border); in amdgpu_atombios_crtc_overscan_setup()
76 args.usOverscanLeft = cpu_to_le16(amdgpu_crtc->h_border); in amdgpu_atombios_crtc_overscan_setup()
77 args.usOverscanBottom = cpu_to_le16(amdgpu_crtc->v_border); in amdgpu_atombios_crtc_overscan_setup()
78 args.usOverscanTop = cpu_to_le16(amdgpu_crtc->v_border); in amdgpu_atombios_crtc_overscan_setup()
81 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); in amdgpu_atombios_crtc_overscan_setup()
86 struct drm_device *dev = crtc->dev; in amdgpu_atombios_crtc_scaler_setup()
94 args.ucScaler = amdgpu_crtc->crtc_id; in amdgpu_atombios_crtc_scaler_setup()
96 switch (amdgpu_crtc->rmx_type) { in amdgpu_atombios_crtc_scaler_setup()
110 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); in amdgpu_atombios_crtc_scaler_setup()
116 struct drm_device *dev = crtc->dev; in amdgpu_atombios_crtc_lock()
124 args.ucCRTC = amdgpu_crtc->crtc_id; in amdgpu_atombios_crtc_lock()
127 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); in amdgpu_atombios_crtc_lock()
133 struct drm_device *dev = crtc->dev; in amdgpu_atombios_crtc_enable()
140 args.ucCRTC = amdgpu_crtc->crtc_id; in amdgpu_atombios_crtc_enable()
143 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); in amdgpu_atombios_crtc_enable()
149 struct drm_device *dev = crtc->dev; in amdgpu_atombios_crtc_blank()
156 args.ucCRTC = amdgpu_crtc->crtc_id; in amdgpu_atombios_crtc_blank()
159 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); in amdgpu_atombios_crtc_blank()
165 struct drm_device *dev = crtc->dev; in amdgpu_atombios_crtc_powergate()
172 args.ucDispPipeId = amdgpu_crtc->crtc_id; in amdgpu_atombios_crtc_powergate()
175 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); in amdgpu_atombios_crtc_powergate()
187 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); in amdgpu_atombios_crtc_powergate_init()
194 struct drm_device *dev = crtc->dev; in amdgpu_atombios_crtc_set_dtd_timing()
201 args.usH_Size = cpu_to_le16(mode->crtc_hdisplay - (amdgpu_crtc->h_border * 2)); in amdgpu_atombios_crtc_set_dtd_timing()
203 cpu_to_le16(mode->crtc_hblank_end - mode->crtc_hdisplay + (amdgpu_crtc->h_border * 2)); in amdgpu_atombios_crtc_set_dtd_timing()
204 args.usV_Size = cpu_to_le16(mode->crtc_vdisplay - (amdgpu_crtc->v_border * 2)); in amdgpu_atombios_crtc_set_dtd_timing()
206 cpu_to_le16(mode->crtc_vblank_end - mode->crtc_vdisplay + (amdgpu_crtc->v_border * 2)); in amdgpu_atombios_crtc_set_dtd_timing()
208 cpu_to_le16(mode->crtc_hsync_start - mode->crtc_hdisplay + amdgpu_crtc->h_border); in amdgpu_atombios_crtc_set_dtd_timing()
210 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start); in amdgpu_atombios_crtc_set_dtd_timing()
212 cpu_to_le16(mode->crtc_vsync_start - mode->crtc_vdisplay + amdgpu_crtc->v_border); in amdgpu_atombios_crtc_set_dtd_timing()
214 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start); in amdgpu_atombios_crtc_set_dtd_timing()
215 args.ucH_Border = amdgpu_crtc->h_border; in amdgpu_atombios_crtc_set_dtd_timing()
216 args.ucV_Border = amdgpu_crtc->v_border; in amdgpu_atombios_crtc_set_dtd_timing()
218 if (mode->flags & DRM_MODE_FLAG_NVSYNC) in amdgpu_atombios_crtc_set_dtd_timing()
220 if (mode->flags & DRM_MODE_FLAG_NHSYNC) in amdgpu_atombios_crtc_set_dtd_timing()
222 if (mode->flags & DRM_MODE_FLAG_CSYNC) in amdgpu_atombios_crtc_set_dtd_timing()
224 if (mode->flags & DRM_MODE_FLAG_INTERLACE) in amdgpu_atombios_crtc_set_dtd_timing()
226 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) in amdgpu_atombios_crtc_set_dtd_timing()
230 args.ucCRTC = amdgpu_crtc->crtc_id; in amdgpu_atombios_crtc_set_dtd_timing()
232 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); in amdgpu_atombios_crtc_set_dtd_timing()
236 ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION v1; member
257 if (ss->percentage == 0) in amdgpu_atombios_crtc_program_ss()
259 if (ss->type & ATOM_EXTERNAL_SS_MASK) in amdgpu_atombios_crtc_program_ss()
262 for (i = 0; i < adev->mode_info.num_crtc; i++) { in amdgpu_atombios_crtc_program_ss()
263 if (adev->mode_info.crtcs[i] && in amdgpu_atombios_crtc_program_ss()
264 adev->mode_info.crtcs[i]->enabled && in amdgpu_atombios_crtc_program_ss()
266 pll_id == adev->mode_info.crtcs[i]->pll_id) { in amdgpu_atombios_crtc_program_ss()
279 args.v3.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; in amdgpu_atombios_crtc_program_ss()
293 args.v3.usSpreadSpectrumAmount = cpu_to_le16(ss->amount); in amdgpu_atombios_crtc_program_ss()
294 args.v3.usSpreadSpectrumStep = cpu_to_le16(ss->step); in amdgpu_atombios_crtc_program_ss()
297 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); in amdgpu_atombios_crtc_program_ss()
301 ADJUST_DISPLAY_PLL_PS_ALLOCATION v1; member
309 struct drm_device *dev = crtc->dev; in amdgpu_atombios_crtc_adjust_pll()
311 struct drm_encoder *encoder = amdgpu_crtc->encoder; in amdgpu_atombios_crtc_adjust_pll()
314 u32 adjusted_clock = mode->clock; in amdgpu_atombios_crtc_adjust_pll()
316 u32 dp_clock = mode->clock; in amdgpu_atombios_crtc_adjust_pll()
317 u32 clock = mode->clock; in amdgpu_atombios_crtc_adjust_pll()
318 int bpc = amdgpu_crtc->bpc; in amdgpu_atombios_crtc_adjust_pll()
319 bool is_duallink = amdgpu_dig_monitor_is_duallink(encoder, mode->clock); in amdgpu_atombios_crtc_adjust_pll()
324 amdgpu_crtc->pll_flags = AMDGPU_PLL_USE_FRAC_FB_DIV; in amdgpu_atombios_crtc_adjust_pll()
326 if ((amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) || in amdgpu_atombios_crtc_adjust_pll()
331 amdgpu_connector->con_priv; in amdgpu_atombios_crtc_adjust_pll()
333 dp_clock = dig_connector->dp_clock; in amdgpu_atombios_crtc_adjust_pll()
338 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { in amdgpu_atombios_crtc_adjust_pll()
339 if (amdgpu_crtc->ss_enabled) { in amdgpu_atombios_crtc_adjust_pll()
340 if (amdgpu_crtc->ss.refdiv) { in amdgpu_atombios_crtc_adjust_pll()
341 amdgpu_crtc->pll_flags |= AMDGPU_PLL_USE_REF_DIV; in amdgpu_atombios_crtc_adjust_pll()
342 amdgpu_crtc->pll_reference_div = amdgpu_crtc->ss.refdiv; in amdgpu_atombios_crtc_adjust_pll()
343 amdgpu_crtc->pll_flags |= AMDGPU_PLL_USE_FRAC_FB_DIV; in amdgpu_atombios_crtc_adjust_pll()
349 if (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1) in amdgpu_atombios_crtc_adjust_pll()
350 adjusted_clock = mode->clock * 2; in amdgpu_atombios_crtc_adjust_pll()
351 if (amdgpu_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) in amdgpu_atombios_crtc_adjust_pll()
352 amdgpu_crtc->pll_flags |= AMDGPU_PLL_PREFER_CLOSEST_LOWER; in amdgpu_atombios_crtc_adjust_pll()
353 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) in amdgpu_atombios_crtc_adjust_pll()
354 amdgpu_crtc->pll_flags |= AMDGPU_PLL_IS_LCD; in amdgpu_atombios_crtc_adjust_pll()
380 if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, in amdgpu_atombios_crtc_adjust_pll()
391 args.v1.usPixelClock = cpu_to_le16(clock / 10); in amdgpu_atombios_crtc_adjust_pll()
392 args.v1.ucTransmitterID = amdgpu_encoder->encoder_id; in amdgpu_atombios_crtc_adjust_pll()
393 args.v1.ucEncodeMode = encoder_mode; in amdgpu_atombios_crtc_adjust_pll()
394 if (amdgpu_crtc->ss_enabled && amdgpu_crtc->ss.percentage) in amdgpu_atombios_crtc_adjust_pll()
395 args.v1.ucConfig |= in amdgpu_atombios_crtc_adjust_pll()
398 amdgpu_atom_execute_table(adev->mode_info.atom_context, in amdgpu_atombios_crtc_adjust_pll()
400 adjusted_clock = le16_to_cpu(args.v1.usPixelClock) * 10; in amdgpu_atombios_crtc_adjust_pll()
404 args.v3.sInput.ucTransmitterID = amdgpu_encoder->encoder_id; in amdgpu_atombios_crtc_adjust_pll()
407 if (amdgpu_crtc->ss_enabled && amdgpu_crtc->ss.percentage) in amdgpu_atombios_crtc_adjust_pll()
415 } else if (amdgpu_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { in amdgpu_atombios_crtc_adjust_pll()
416 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in amdgpu_atombios_crtc_adjust_pll()
417 if (dig->coherent_mode) in amdgpu_atombios_crtc_adjust_pll()
431 amdgpu_atom_execute_table(adev->mode_info.atom_context, in amdgpu_atombios_crtc_adjust_pll()
435 amdgpu_crtc->pll_flags |= AMDGPU_PLL_USE_FRAC_FB_DIV; in amdgpu_atombios_crtc_adjust_pll()
436 amdgpu_crtc->pll_flags |= AMDGPU_PLL_USE_REF_DIV; in amdgpu_atombios_crtc_adjust_pll()
437 amdgpu_crtc->pll_reference_div = args.v3.sOutput.ucRefDiv; in amdgpu_atombios_crtc_adjust_pll()
440 amdgpu_crtc->pll_flags |= AMDGPU_PLL_USE_FRAC_FB_DIV; in amdgpu_atombios_crtc_adjust_pll()
441 amdgpu_crtc->pll_flags |= AMDGPU_PLL_USE_POST_DIV; in amdgpu_atombios_crtc_adjust_pll()
442 amdgpu_crtc->pll_post_div = args.v3.sOutput.ucPostDiv; in amdgpu_atombios_crtc_adjust_pll()
460 PIXEL_CLOCK_PARAMETERS v1; member
464 PIXEL_CLOCK_PARAMETERS_V6 v6; member
481 if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, in amdgpu_atombios_crtc_set_disp_eng_pll()
500 args.v6.ulDispEngClkFreq = cpu_to_le32(dispclk); in amdgpu_atombios_crtc_set_disp_eng_pll()
501 if (adev->asic_type == CHIP_TAHITI || in amdgpu_atombios_crtc_set_disp_eng_pll()
502 adev->asic_type == CHIP_PITCAIRN || in amdgpu_atombios_crtc_set_disp_eng_pll()
503 adev->asic_type == CHIP_VERDE || in amdgpu_atombios_crtc_set_disp_eng_pll()
504 adev->asic_type == CHIP_OLAND) in amdgpu_atombios_crtc_set_disp_eng_pll()
505 args.v6.ucPpll = ATOM_PPLL0; in amdgpu_atombios_crtc_set_disp_eng_pll()
507 args.v6.ucPpll = ATOM_EXT_PLL1; in amdgpu_atombios_crtc_set_disp_eng_pll()
518 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); in amdgpu_atombios_crtc_set_disp_eng_pll()
537 if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, in amdgpu_atombios_crtc_set_dce_clock()
548 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); in amdgpu_atombios_crtc_set_dce_clock()
590 struct drm_device *dev = crtc->dev; in amdgpu_atombios_crtc_program_pll()
598 if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, in amdgpu_atombios_crtc_program_pll()
608 args.v1.usPixelClock = cpu_to_le16(clock / 10); in amdgpu_atombios_crtc_program_pll()
609 args.v1.usRefDiv = cpu_to_le16(ref_div); in amdgpu_atombios_crtc_program_pll()
610 args.v1.usFbDiv = cpu_to_le16(fb_div); in amdgpu_atombios_crtc_program_pll()
611 args.v1.ucFracFbDiv = frac_fb_div; in amdgpu_atombios_crtc_program_pll()
612 args.v1.ucPostDiv = post_div; in amdgpu_atombios_crtc_program_pll()
613 args.v1.ucPpll = pll_id; in amdgpu_atombios_crtc_program_pll()
614 args.v1.ucCRTC = crtc_id; in amdgpu_atombios_crtc_program_pll()
615 args.v1.ucRefDivSrc = 1; in amdgpu_atombios_crtc_program_pll()
638 if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK)) in amdgpu_atombios_crtc_program_pll()
651 if ((ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK)) && in amdgpu_atombios_crtc_program_pll()
675 args.v6.ulDispEngClkFreq = cpu_to_le32(crtc_id << 24 | clock / 10); in amdgpu_atombios_crtc_program_pll()
676 args.v6.ucRefDiv = ref_div; in amdgpu_atombios_crtc_program_pll()
677 args.v6.usFbDiv = cpu_to_le16(fb_div); in amdgpu_atombios_crtc_program_pll()
678 args.v6.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000); in amdgpu_atombios_crtc_program_pll()
679 args.v6.ucPostDiv = post_div; in amdgpu_atombios_crtc_program_pll()
680 args.v6.ucMiscInfo = 0; /* HDMI depth, etc. */ in amdgpu_atombios_crtc_program_pll()
681 if ((ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK)) && in amdgpu_atombios_crtc_program_pll()
684 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_REF_DIV_SRC; in amdgpu_atombios_crtc_program_pll()
689 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_24BPP; in amdgpu_atombios_crtc_program_pll()
692 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_30BPP_V6; in amdgpu_atombios_crtc_program_pll()
695 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_36BPP_V6; in amdgpu_atombios_crtc_program_pll()
698 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_48BPP; in amdgpu_atombios_crtc_program_pll()
702 args.v6.ucTransmitterID = encoder_id; in amdgpu_atombios_crtc_program_pll()
703 args.v6.ucEncoderMode = encoder_mode; in amdgpu_atombios_crtc_program_pll()
704 args.v6.ucPpll = pll_id; in amdgpu_atombios_crtc_program_pll()
744 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); in amdgpu_atombios_crtc_program_pll()
751 struct drm_device *dev = crtc->dev; in amdgpu_atombios_crtc_prepare_pll()
754 to_amdgpu_encoder(amdgpu_crtc->encoder); in amdgpu_atombios_crtc_prepare_pll()
755 int encoder_mode = amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder); in amdgpu_atombios_crtc_prepare_pll()
757 amdgpu_crtc->bpc = 8; in amdgpu_atombios_crtc_prepare_pll()
758 amdgpu_crtc->ss_enabled = false; in amdgpu_atombios_crtc_prepare_pll()
760 if ((amdgpu_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) || in amdgpu_atombios_crtc_prepare_pll()
761 (amdgpu_encoder_get_dp_bridge_encoder_id(amdgpu_crtc->encoder) != ENCODER_OBJECT_ID_NONE)) { in amdgpu_atombios_crtc_prepare_pll()
762 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in amdgpu_atombios_crtc_prepare_pll()
764 amdgpu_get_connector_for_encoder(amdgpu_crtc->encoder); in amdgpu_atombios_crtc_prepare_pll()
768 amdgpu_connector->con_priv; in amdgpu_atombios_crtc_prepare_pll()
772 amdgpu_connector->pixelclock_for_modeset = mode->clock; in amdgpu_atombios_crtc_prepare_pll()
773 amdgpu_crtc->bpc = amdgpu_connector_get_monitor_bpc(connector); in amdgpu_atombios_crtc_prepare_pll()
779 dp_clock = dig_connector->dp_clock / 10; in amdgpu_atombios_crtc_prepare_pll()
780 amdgpu_crtc->ss_enabled = in amdgpu_atombios_crtc_prepare_pll()
781 amdgpu_atombios_get_asic_ss_info(adev, &amdgpu_crtc->ss, in amdgpu_atombios_crtc_prepare_pll()
786 amdgpu_crtc->ss_enabled = in amdgpu_atombios_crtc_prepare_pll()
788 &amdgpu_crtc->ss, in amdgpu_atombios_crtc_prepare_pll()
789 dig->lcd_ss_id, in amdgpu_atombios_crtc_prepare_pll()
790 mode->clock / 10); in amdgpu_atombios_crtc_prepare_pll()
793 amdgpu_crtc->ss_enabled = in amdgpu_atombios_crtc_prepare_pll()
795 &amdgpu_crtc->ss, in amdgpu_atombios_crtc_prepare_pll()
797 mode->clock / 10); in amdgpu_atombios_crtc_prepare_pll()
800 amdgpu_crtc->ss_enabled = in amdgpu_atombios_crtc_prepare_pll()
802 &amdgpu_crtc->ss, in amdgpu_atombios_crtc_prepare_pll()
804 mode->clock / 10); in amdgpu_atombios_crtc_prepare_pll()
812 amdgpu_crtc->adjusted_clock = amdgpu_atombios_crtc_adjust_pll(crtc, mode); in amdgpu_atombios_crtc_prepare_pll()
820 struct drm_device *dev = crtc->dev; in amdgpu_atombios_crtc_set_pll()
823 to_amdgpu_encoder(amdgpu_crtc->encoder); in amdgpu_atombios_crtc_set_pll()
824 u32 pll_clock = mode->clock; in amdgpu_atombios_crtc_set_pll()
825 u32 clock = mode->clock; in amdgpu_atombios_crtc_set_pll()
828 int encoder_mode = amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder); in amdgpu_atombios_crtc_set_pll()
832 (amdgpu_crtc->bpc > 8)) in amdgpu_atombios_crtc_set_pll()
833 clock = amdgpu_crtc->adjusted_clock; in amdgpu_atombios_crtc_set_pll()
835 switch (amdgpu_crtc->pll_id) { in amdgpu_atombios_crtc_set_pll()
837 pll = &adev->clock.ppll[0]; in amdgpu_atombios_crtc_set_pll()
840 pll = &adev->clock.ppll[1]; in amdgpu_atombios_crtc_set_pll()
845 pll = &adev->clock.ppll[2]; in amdgpu_atombios_crtc_set_pll()
850 pll->flags = amdgpu_crtc->pll_flags; in amdgpu_atombios_crtc_set_pll()
851 pll->reference_div = amdgpu_crtc->pll_reference_div; in amdgpu_atombios_crtc_set_pll()
852 pll->post_div = amdgpu_crtc->pll_post_div; in amdgpu_atombios_crtc_set_pll()
854 amdgpu_pll_compute(adev, pll, amdgpu_crtc->adjusted_clock, &pll_clock, in amdgpu_atombios_crtc_set_pll()
857 amdgpu_atombios_crtc_program_ss(adev, ATOM_DISABLE, amdgpu_crtc->pll_id, in amdgpu_atombios_crtc_set_pll()
858 amdgpu_crtc->crtc_id, &amdgpu_crtc->ss); in amdgpu_atombios_crtc_set_pll()
860 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id, in amdgpu_atombios_crtc_set_pll()
861 encoder_mode, amdgpu_encoder->encoder_id, clock, in amdgpu_atombios_crtc_set_pll()
863 amdgpu_crtc->bpc, amdgpu_crtc->ss_enabled, &amdgpu_crtc->ss); in amdgpu_atombios_crtc_set_pll()
865 if (amdgpu_crtc->ss_enabled) { in amdgpu_atombios_crtc_set_pll()
869 (u32)amdgpu_crtc->ss.percentage) / in amdgpu_atombios_crtc_set_pll()
870 (100 * (u32)amdgpu_crtc->ss.percentage_divider); in amdgpu_atombios_crtc_set_pll()
871 amdgpu_crtc->ss.amount = (amount / 10) & ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK; in amdgpu_atombios_crtc_set_pll()
872 amdgpu_crtc->ss.amount |= ((amount - (amount / 10)) << ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT) & in amdgpu_atombios_crtc_set_pll()
874 if (amdgpu_crtc->ss.type & ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD) in amdgpu_atombios_crtc_set_pll()
875 step_size = (4 * amount * ref_div * ((u32)amdgpu_crtc->ss.rate * 2048)) / in amdgpu_atombios_crtc_set_pll()
876 (125 * 25 * pll->reference_freq / 100); in amdgpu_atombios_crtc_set_pll()
878 step_size = (2 * amount * ref_div * ((u32)amdgpu_crtc->ss.rate * 2048)) / in amdgpu_atombios_crtc_set_pll()
879 (125 * 25 * pll->reference_freq / 100); in amdgpu_atombios_crtc_set_pll()
880 amdgpu_crtc->ss.step = step_size; in amdgpu_atombios_crtc_set_pll()
882 amdgpu_atombios_crtc_program_ss(adev, ATOM_ENABLE, amdgpu_crtc->pll_id, in amdgpu_atombios_crtc_set_pll()
883 amdgpu_crtc->crtc_id, &amdgpu_crtc->ss); in amdgpu_atombios_crtc_set_pll()