82 	int (*req_full_gpu)(struct amdgpu_device *adev, bool init);
83 	int (*rel_full_gpu)(struct amdgpu_device *adev, bool init);
84 	int (*req_init_data)(struct amdgpu_device *adev);
85 	int (*reset_gpu)(struct amdgpu_device *adev);
86 	int (*wait_reset)(struct amdgpu_device *adev);
87 	void (*trans_msg)(struct amdgpu_device *adev, u32 req, u32 data1, u32 data2, u32 data3);
264 #define amdgpu_sriov_enabled(adev) \  argument
265 ((adev)->virt.caps & AMDGPU_SRIOV_CAPS_ENABLE_IOV)
267 #define amdgpu_sriov_vf(adev) \  argument
268 ((adev)->virt.caps & AMDGPU_SRIOV_CAPS_IS_VF)
270 #define amdgpu_sriov_bios(adev) \  argument
271 ((adev)->virt.caps & AMDGPU_SRIOV_CAPS_SRIOV_VBIOS)
273 #define amdgpu_sriov_runtime(adev) \  argument
274 ((adev)->virt.caps & AMDGPU_SRIOV_CAPS_RUNTIME)
276 #define amdgpu_sriov_fullaccess(adev) \  argument
277 (amdgpu_sriov_vf((adev)) && !amdgpu_sriov_runtime((adev)))
279 #define amdgpu_sriov_reg_indirect_en(adev) \  argument
280 (amdgpu_sriov_vf((adev)) && \
281 	((adev)->virt.gim_feature & (AMDGIM_FEATURE_INDIRECT_REG_ACCESS)))
283 #define amdgpu_sriov_reg_indirect_ih(adev) \  argument
284 (amdgpu_sriov_vf((adev)) && \
285 	((adev)->virt.reg_access & (AMDGIM_FEATURE_IH_REG_PSP_EN)))
287 #define amdgpu_sriov_reg_indirect_mmhub(adev) \  argument
288 (amdgpu_sriov_vf((adev)) && \
289 	((adev)->virt.reg_access & (AMDGIM_FEATURE_MMHUB_REG_RLC_EN)))
291 #define amdgpu_sriov_reg_indirect_gc(adev) \  argument
292 (amdgpu_sriov_vf((adev)) && \
293 	((adev)->virt.reg_access & (AMDGIM_FEATURE_GC_REG_RLC_EN)))
295 #define amdgpu_sriov_rlcg_error_report_enabled(adev) \  argument
296         (amdgpu_sriov_reg_indirect_mmhub(adev) || amdgpu_sriov_reg_indirect_gc(adev))
298 #define amdgpu_passthrough(adev) \  argument
299 ((adev)->virt.caps & AMDGPU_PASSTHROUGH_MODE)
301 #define amdgpu_sriov_vf_mmio_access_protection(adev) \  argument
302 ((adev)->virt.caps & AMDGPU_VF_MMIO_ACCESS_PROTECT)
315 #define amdgpu_sriov_is_pp_one_vf(adev) \  argument
316 	((adev)->virt.gim_feature & AMDGIM_FEATURE_PP_ONE_VF)
317 #define amdgpu_sriov_is_debug(adev) \  argument
318 	((!amdgpu_in_reset(adev)) && adev->virt.tdr_debug)
319 #define amdgpu_sriov_is_normal(adev) \  argument
320 	((!amdgpu_in_reset(adev)) && (!adev->virt.tdr_debug))
321 bool amdgpu_virt_mmio_blocked(struct amdgpu_device *adev);
322 void amdgpu_virt_init_setting(struct amdgpu_device *adev);
323 void amdgpu_virt_kiq_reg_write_reg_wait(struct amdgpu_device *adev,
326 int amdgpu_virt_request_full_gpu(struct amdgpu_device *adev, bool init);
327 int amdgpu_virt_release_full_gpu(struct amdgpu_device *adev, bool init);
328 int amdgpu_virt_reset_gpu(struct amdgpu_device *adev);
329 void amdgpu_virt_request_init_data(struct amdgpu_device *adev);
330 int amdgpu_virt_wait_reset(struct amdgpu_device *adev);
331 int amdgpu_virt_alloc_mm_table(struct amdgpu_device *adev);
332 void amdgpu_virt_free_mm_table(struct amdgpu_device *adev);
333 void amdgpu_virt_release_ras_err_handler_data(struct amdgpu_device *adev);
334 void amdgpu_virt_init_data_exchange(struct amdgpu_device *adev);
335 void amdgpu_virt_exchange_data(struct amdgpu_device *adev);
336 void amdgpu_virt_fini_data_exchange(struct amdgpu_device *adev);
337 void amdgpu_detect_virtualization(struct amdgpu_device *adev);
339 bool amdgpu_virt_can_access_debugfs(struct amdgpu_device *adev);
340 int amdgpu_virt_enable_access_debugfs(struct amdgpu_device *adev);
341 void amdgpu_virt_disable_access_debugfs(struct amdgpu_device *adev);
343 enum amdgpu_sriov_vf_mode amdgpu_virt_get_sriov_vf_mode(struct amdgpu_device *adev);
345 void amdgpu_virt_update_sriov_video_codec(struct amdgpu_device *adev,
348 void amdgpu_sriov_wreg(struct amdgpu_device *adev,
351 u32 amdgpu_sriov_rreg(struct amdgpu_device *adev,
353 bool amdgpu_virt_fw_load_skip_check(struct amdgpu_device *adev,