314 		const struct sdma_firmware_header_v1_0 *sdma_hdr =  in amdgpu_ucode_print_sdma_hdr()  local
318 			  le32_to_cpu(sdma_hdr->ucode_feature_version));  in amdgpu_ucode_print_sdma_hdr()
320 			  le32_to_cpu(sdma_hdr->ucode_change_version));  in amdgpu_ucode_print_sdma_hdr()
321 		DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(sdma_hdr->jt_offset));  in amdgpu_ucode_print_sdma_hdr()
322 		DRM_DEBUG("jt_size: %u\n", le32_to_cpu(sdma_hdr->jt_size));  in amdgpu_ucode_print_sdma_hdr()
325 				container_of(sdma_hdr, struct sdma_firmware_header_v1_1, v1_0);  in amdgpu_ucode_print_sdma_hdr()
329 		const struct sdma_firmware_header_v2_0 *sdma_hdr =  in amdgpu_ucode_print_sdma_hdr()  local
333 			  le32_to_cpu(sdma_hdr->ucode_feature_version));  in amdgpu_ucode_print_sdma_hdr()
334 		DRM_DEBUG("ctx_jt_offset: %u\n", le32_to_cpu(sdma_hdr->ctx_jt_offset));  in amdgpu_ucode_print_sdma_hdr()
335 		DRM_DEBUG("ctx_jt_size: %u\n", le32_to_cpu(sdma_hdr->ctx_jt_size));  in amdgpu_ucode_print_sdma_hdr()
336 		DRM_DEBUG("ctl_ucode_offset: %u\n", le32_to_cpu(sdma_hdr->ctl_ucode_offset));  in amdgpu_ucode_print_sdma_hdr()
337 		DRM_DEBUG("ctl_jt_offset: %u\n", le32_to_cpu(sdma_hdr->ctl_jt_offset));  in amdgpu_ucode_print_sdma_hdr()
338 		DRM_DEBUG("ctl_jt_size: %u\n", le32_to_cpu(sdma_hdr->ctl_jt_size));  in amdgpu_ucode_print_sdma_hdr()
752 	const struct sdma_firmware_header_v2_0 *sdma_hdr = NULL;  in amdgpu_ucode_init_single_fw()  local
771 	sdma_hdr = (const struct sdma_firmware_header_v2_0 *)ucode->fw->data;  in amdgpu_ucode_init_single_fw()
777 			ucode->ucode_size = le32_to_cpu(sdma_hdr->ctx_ucode_size_bytes);  in amdgpu_ucode_init_single_fw()
779 				le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes);  in amdgpu_ucode_init_single_fw()
782 			ucode->ucode_size = le32_to_cpu(sdma_hdr->ctl_ucode_size_bytes);  in amdgpu_ucode_init_single_fw()
784 				le32_to_cpu(sdma_hdr->ctl_ucode_offset);  in amdgpu_ucode_init_single_fw()