33 	DRM_DEBUG("size_bytes: %u\n", le32_to_cpu(hdr->size_bytes));  in amdgpu_ucode_print_common_hdr()
34 	DRM_DEBUG("header_size_bytes: %u\n", le32_to_cpu(hdr->header_size_bytes));  in amdgpu_ucode_print_common_hdr()
35 	DRM_DEBUG("header_version_major: %u\n", le16_to_cpu(hdr->header_version_major));  in amdgpu_ucode_print_common_hdr()
36 	DRM_DEBUG("header_version_minor: %u\n", le16_to_cpu(hdr->header_version_minor));  in amdgpu_ucode_print_common_hdr()
37 	DRM_DEBUG("ip_version_major: %u\n", le16_to_cpu(hdr->ip_version_major));  in amdgpu_ucode_print_common_hdr()
38 	DRM_DEBUG("ip_version_minor: %u\n", le16_to_cpu(hdr->ip_version_minor));  in amdgpu_ucode_print_common_hdr()
39 	DRM_DEBUG("ucode_version: 0x%08x\n", le32_to_cpu(hdr->ucode_version));  in amdgpu_ucode_print_common_hdr()
40 	DRM_DEBUG("ucode_size_bytes: %u\n", le32_to_cpu(hdr->ucode_size_bytes));  in amdgpu_ucode_print_common_hdr()
41 	DRM_DEBUG("ucode_array_offset_bytes: %u\n",  in amdgpu_ucode_print_common_hdr()
43 	DRM_DEBUG("crc32: 0x%08x\n", le32_to_cpu(hdr->crc32));  in amdgpu_ucode_print_common_hdr()
51 	DRM_DEBUG("MC\n");  in amdgpu_ucode_print_mc_hdr()
58 		DRM_DEBUG("io_debug_size_bytes: %u\n",  in amdgpu_ucode_print_mc_hdr()
60 		DRM_DEBUG("io_debug_array_offset_bytes: %u\n",  in amdgpu_ucode_print_mc_hdr()
75 	DRM_DEBUG("SMC\n");  in amdgpu_ucode_print_smc_hdr()
80 		DRM_DEBUG("ucode_start_addr: %u\n", le32_to_cpu(v1_0_hdr->ucode_start_addr));  in amdgpu_ucode_print_smc_hdr()
85 			DRM_DEBUG("ppt_offset_bytes: %u\n", le32_to_cpu(v2_0_hdr->ppt_offset_bytes));  in amdgpu_ucode_print_smc_hdr()
86 			DRM_DEBUG("ppt_size_bytes: %u\n", le32_to_cpu(v2_0_hdr->ppt_size_bytes));  in amdgpu_ucode_print_smc_hdr()
90 			DRM_DEBUG("pptable_count: %u\n", le32_to_cpu(v2_1_hdr->pptable_count));  in amdgpu_ucode_print_smc_hdr()
91 			DRM_DEBUG("pptable_entry_offset: %u\n", le32_to_cpu(v2_1_hdr->pptable_entry_offset));  in amdgpu_ucode_print_smc_hdr()
107 	DRM_DEBUG("GFX\n");  in amdgpu_ucode_print_gfx_hdr()
114 		DRM_DEBUG("ucode_feature_version: %u\n",  in amdgpu_ucode_print_gfx_hdr()
116 		DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(gfx_hdr->jt_offset));  in amdgpu_ucode_print_gfx_hdr()
117 		DRM_DEBUG("jt_size: %u\n", le32_to_cpu(gfx_hdr->jt_size));  in amdgpu_ucode_print_gfx_hdr()
122 		DRM_DEBUG("ucode_feature_version: %u\n",  in amdgpu_ucode_print_gfx_hdr()
134 	DRM_DEBUG("IMU\n");  in amdgpu_ucode_print_imu_hdr()
147 	DRM_DEBUG("RLC\n");  in amdgpu_ucode_print_rlc_hdr()
154 		DRM_DEBUG("ucode_feature_version: %u\n",  in amdgpu_ucode_print_rlc_hdr()
156 		DRM_DEBUG("save_and_restore_offset: %u\n",  in amdgpu_ucode_print_rlc_hdr()
158 		DRM_DEBUG("clear_state_descriptor_offset: %u\n",  in amdgpu_ucode_print_rlc_hdr()
160 		DRM_DEBUG("avail_scratch_ram_locations: %u\n",  in amdgpu_ucode_print_rlc_hdr()
162 		DRM_DEBUG("master_pkt_description_offset: %u\n",  in amdgpu_ucode_print_rlc_hdr()
179 			DRM_DEBUG("ucode_feature_version: %u\n",  in amdgpu_ucode_print_rlc_hdr()
181 			DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(rlc_hdr->jt_offset));  in amdgpu_ucode_print_rlc_hdr()
182 			DRM_DEBUG("jt_size: %u\n", le32_to_cpu(rlc_hdr->jt_size));  in amdgpu_ucode_print_rlc_hdr()
183 			DRM_DEBUG("save_and_restore_offset: %u\n",  in amdgpu_ucode_print_rlc_hdr()
185 			DRM_DEBUG("clear_state_descriptor_offset: %u\n",  in amdgpu_ucode_print_rlc_hdr()
187 			DRM_DEBUG("avail_scratch_ram_locations: %u\n",  in amdgpu_ucode_print_rlc_hdr()
189 			DRM_DEBUG("reg_restore_list_size: %u\n",  in amdgpu_ucode_print_rlc_hdr()
191 			DRM_DEBUG("reg_list_format_start: %u\n",  in amdgpu_ucode_print_rlc_hdr()
193 			DRM_DEBUG("reg_list_format_separate_start: %u\n",  in amdgpu_ucode_print_rlc_hdr()
195 			DRM_DEBUG("starting_offsets_start: %u\n",  in amdgpu_ucode_print_rlc_hdr()
197 			DRM_DEBUG("reg_list_format_size_bytes: %u\n",  in amdgpu_ucode_print_rlc_hdr()
199 			DRM_DEBUG("reg_list_format_array_offset_bytes: %u\n",  in amdgpu_ucode_print_rlc_hdr()
201 			DRM_DEBUG("reg_list_size_bytes: %u\n",  in amdgpu_ucode_print_rlc_hdr()
203 			DRM_DEBUG("reg_list_array_offset_bytes: %u\n",  in amdgpu_ucode_print_rlc_hdr()
205 			DRM_DEBUG("reg_list_format_separate_size_bytes: %u\n",  in amdgpu_ucode_print_rlc_hdr()
207 			DRM_DEBUG("reg_list_format_separate_array_offset_bytes: %u\n",  in amdgpu_ucode_print_rlc_hdr()
209 			DRM_DEBUG("reg_list_separate_size_bytes: %u\n",  in amdgpu_ucode_print_rlc_hdr()
211 			DRM_DEBUG("reg_list_separate_array_offset_bytes: %u\n",  in amdgpu_ucode_print_rlc_hdr()
216 			DRM_DEBUG("reg_list_format_direct_reg_list_length: %u\n",  in amdgpu_ucode_print_rlc_hdr()
218 			DRM_DEBUG("save_restore_list_cntl_ucode_ver: %u\n",  in amdgpu_ucode_print_rlc_hdr()
220 			DRM_DEBUG("save_restore_list_cntl_feature_ver: %u\n",  in amdgpu_ucode_print_rlc_hdr()
222 			DRM_DEBUG("save_restore_list_cntl_size_bytes %u\n",  in amdgpu_ucode_print_rlc_hdr()
224 			DRM_DEBUG("save_restore_list_cntl_offset_bytes: %u\n",  in amdgpu_ucode_print_rlc_hdr()
226 			DRM_DEBUG("save_restore_list_gpm_ucode_ver: %u\n",  in amdgpu_ucode_print_rlc_hdr()
228 			DRM_DEBUG("save_restore_list_gpm_feature_ver: %u\n",  in amdgpu_ucode_print_rlc_hdr()
230 			DRM_DEBUG("save_restore_list_gpm_size_bytes %u\n",  in amdgpu_ucode_print_rlc_hdr()
232 			DRM_DEBUG("save_restore_list_gpm_offset_bytes: %u\n",  in amdgpu_ucode_print_rlc_hdr()
234 			DRM_DEBUG("save_restore_list_srm_ucode_ver: %u\n",  in amdgpu_ucode_print_rlc_hdr()
236 			DRM_DEBUG("save_restore_list_srm_feature_ver: %u\n",  in amdgpu_ucode_print_rlc_hdr()
238 			DRM_DEBUG("save_restore_list_srm_size_bytes %u\n",  in amdgpu_ucode_print_rlc_hdr()
240 			DRM_DEBUG("save_restore_list_srm_offset_bytes: %u\n",  in amdgpu_ucode_print_rlc_hdr()
245 			DRM_DEBUG("rlc_iram_ucode_size_bytes: %u\n",  in amdgpu_ucode_print_rlc_hdr()
247 			DRM_DEBUG("rlc_iram_ucode_offset_bytes: %u\n",  in amdgpu_ucode_print_rlc_hdr()
249 			DRM_DEBUG("rlc_dram_ucode_size_bytes: %u\n",  in amdgpu_ucode_print_rlc_hdr()
251 			DRM_DEBUG("rlc_dram_ucode_offset_bytes: %u\n",  in amdgpu_ucode_print_rlc_hdr()
256 			DRM_DEBUG("rlcp_ucode_version: %u\n",  in amdgpu_ucode_print_rlc_hdr()
258 			DRM_DEBUG("rlcp_ucode_feature_version: %u\n",  in amdgpu_ucode_print_rlc_hdr()
260 			DRM_DEBUG("rlcp_ucode_size_bytes: %u\n",  in amdgpu_ucode_print_rlc_hdr()
262 			DRM_DEBUG("rlcp_ucode_offset_bytes: %u\n",  in amdgpu_ucode_print_rlc_hdr()
264 			DRM_DEBUG("rlcv_ucode_version: %u\n",  in amdgpu_ucode_print_rlc_hdr()
266 			DRM_DEBUG("rlcv_ucode_feature_version: %u\n",  in amdgpu_ucode_print_rlc_hdr()
268 			DRM_DEBUG("rlcv_ucode_size_bytes: %u\n",  in amdgpu_ucode_print_rlc_hdr()
270 			DRM_DEBUG("rlcv_ucode_offset_bytes: %u\n",  in amdgpu_ucode_print_rlc_hdr()
275 			DRM_DEBUG("global_tap_delays_ucode_size_bytes :%u\n",  in amdgpu_ucode_print_rlc_hdr()
277 			DRM_DEBUG("global_tap_delays_ucode_offset_bytes: %u\n",  in amdgpu_ucode_print_rlc_hdr()
279 			DRM_DEBUG("se0_tap_delays_ucode_size_bytes :%u\n",  in amdgpu_ucode_print_rlc_hdr()
281 			DRM_DEBUG("se0_tap_delays_ucode_offset_bytes: %u\n",  in amdgpu_ucode_print_rlc_hdr()
283 			DRM_DEBUG("se1_tap_delays_ucode_size_bytes :%u\n",  in amdgpu_ucode_print_rlc_hdr()
285 			DRM_DEBUG("se1_tap_delays_ucode_offset_bytes: %u\n",  in amdgpu_ucode_print_rlc_hdr()
287 			DRM_DEBUG("se2_tap_delays_ucode_size_bytes :%u\n",  in amdgpu_ucode_print_rlc_hdr()
289 			DRM_DEBUG("se2_tap_delays_ucode_offset_bytes: %u\n",  in amdgpu_ucode_print_rlc_hdr()
291 			DRM_DEBUG("se3_tap_delays_ucode_size_bytes :%u\n",  in amdgpu_ucode_print_rlc_hdr()
293 			DRM_DEBUG("se3_tap_delays_ucode_offset_bytes: %u\n",  in amdgpu_ucode_print_rlc_hdr()
310 	DRM_DEBUG("SDMA\n");  in amdgpu_ucode_print_sdma_hdr()
317 		DRM_DEBUG("ucode_feature_version: %u\n",  in amdgpu_ucode_print_sdma_hdr()
319 		DRM_DEBUG("ucode_change_version: %u\n",  in amdgpu_ucode_print_sdma_hdr()
321 		DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(sdma_hdr->jt_offset));  in amdgpu_ucode_print_sdma_hdr()
322 		DRM_DEBUG("jt_size: %u\n", le32_to_cpu(sdma_hdr->jt_size));  in amdgpu_ucode_print_sdma_hdr()
326 			DRM_DEBUG("digest_size: %u\n", le32_to_cpu(sdma_v1_1_hdr->digest_size));  in amdgpu_ucode_print_sdma_hdr()
332 		DRM_DEBUG("ucode_feature_version: %u\n",  in amdgpu_ucode_print_sdma_hdr()
334 		DRM_DEBUG("ctx_jt_offset: %u\n", le32_to_cpu(sdma_hdr->ctx_jt_offset));  in amdgpu_ucode_print_sdma_hdr()
335 		DRM_DEBUG("ctx_jt_size: %u\n", le32_to_cpu(sdma_hdr->ctx_jt_size));  in amdgpu_ucode_print_sdma_hdr()
336 		DRM_DEBUG("ctl_ucode_offset: %u\n", le32_to_cpu(sdma_hdr->ctl_ucode_offset));  in amdgpu_ucode_print_sdma_hdr()
337 		DRM_DEBUG("ctl_jt_offset: %u\n", le32_to_cpu(sdma_hdr->ctl_jt_offset));  in amdgpu_ucode_print_sdma_hdr()
338 		DRM_DEBUG("ctl_jt_size: %u\n", le32_to_cpu(sdma_hdr->ctl_jt_size));  in amdgpu_ucode_print_sdma_hdr()
352 	DRM_DEBUG("PSP\n");  in amdgpu_ucode_print_psp_hdr()
359 		DRM_DEBUG("ucode_feature_version: %u\n",  in amdgpu_ucode_print_psp_hdr()
361 		DRM_DEBUG("sos_offset_bytes: %u\n",  in amdgpu_ucode_print_psp_hdr()
363 		DRM_DEBUG("sos_size_bytes: %u\n",  in amdgpu_ucode_print_psp_hdr()
368 			DRM_DEBUG("toc_header_version: %u\n",  in amdgpu_ucode_print_psp_hdr()
370 			DRM_DEBUG("toc_offset_bytes: %u\n",  in amdgpu_ucode_print_psp_hdr()
372 			DRM_DEBUG("toc_size_bytes: %u\n",  in amdgpu_ucode_print_psp_hdr()
374 			DRM_DEBUG("kdb_header_version: %u\n",  in amdgpu_ucode_print_psp_hdr()
376 			DRM_DEBUG("kdb_offset_bytes: %u\n",  in amdgpu_ucode_print_psp_hdr()
378 			DRM_DEBUG("kdb_size_bytes: %u\n",  in amdgpu_ucode_print_psp_hdr()
384 			DRM_DEBUG("kdb_header_version: %u\n",  in amdgpu_ucode_print_psp_hdr()
386 			DRM_DEBUG("kdb_offset_bytes: %u\n",  in amdgpu_ucode_print_psp_hdr()
388 			DRM_DEBUG("kdb_size_bytes: %u\n",  in amdgpu_ucode_print_psp_hdr()
396 			DRM_DEBUG("toc_header_version: %u\n",  in amdgpu_ucode_print_psp_hdr()
398 			DRM_DEBUG("toc_offset_bytes: %u\n",  in amdgpu_ucode_print_psp_hdr()
400 			DRM_DEBUG("toc_size_bytes: %u\n",  in amdgpu_ucode_print_psp_hdr()
402 			DRM_DEBUG("kdb_header_version: %u\n",  in amdgpu_ucode_print_psp_hdr()
404 			DRM_DEBUG("kdb_offset_bytes: %u\n",  in amdgpu_ucode_print_psp_hdr()
406 			DRM_DEBUG("kdb_size_bytes: %u\n",  in amdgpu_ucode_print_psp_hdr()
408 			DRM_DEBUG("spl_header_version: %u\n",  in amdgpu_ucode_print_psp_hdr()
410 			DRM_DEBUG("spl_offset_bytes: %u\n",  in amdgpu_ucode_print_psp_hdr()
412 			DRM_DEBUG("spl_size_bytes: %u\n",  in amdgpu_ucode_print_psp_hdr()
422 				DRM_DEBUG("psp_sos_version: %u\n",  in amdgpu_ucode_print_psp_hdr()
424 				DRM_DEBUG("psp_sos_size_bytes: %u\n",  in amdgpu_ucode_print_psp_hdr()
428 				DRM_DEBUG("psp_sys_drv_version: %u\n",  in amdgpu_ucode_print_psp_hdr()
430 				DRM_DEBUG("psp_sys_drv_size_bytes: %u\n",  in amdgpu_ucode_print_psp_hdr()
434 				DRM_DEBUG("psp_kdb_version: %u\n",  in amdgpu_ucode_print_psp_hdr()
436 				DRM_DEBUG("psp_kdb_size_bytes: %u\n",  in amdgpu_ucode_print_psp_hdr()
440 				DRM_DEBUG("psp_toc_version: %u\n",  in amdgpu_ucode_print_psp_hdr()
442 				DRM_DEBUG("psp_toc_size_bytes: %u\n",  in amdgpu_ucode_print_psp_hdr()
446 				DRM_DEBUG("psp_spl_version: %u\n",  in amdgpu_ucode_print_psp_hdr()
448 				DRM_DEBUG("psp_spl_size_bytes: %u\n",  in amdgpu_ucode_print_psp_hdr()
452 				DRM_DEBUG("psp_rl_version: %u\n",  in amdgpu_ucode_print_psp_hdr()
454 				DRM_DEBUG("psp_rl_size_bytes: %u\n",  in amdgpu_ucode_print_psp_hdr()
458 				DRM_DEBUG("psp_soc_drv_version: %u\n",  in amdgpu_ucode_print_psp_hdr()
460 				DRM_DEBUG("psp_soc_drv_size_bytes: %u\n",  in amdgpu_ucode_print_psp_hdr()
464 				DRM_DEBUG("psp_intf_drv_version: %u\n",  in amdgpu_ucode_print_psp_hdr()
466 				DRM_DEBUG("psp_intf_drv_size_bytes: %u\n",  in amdgpu_ucode_print_psp_hdr()
470 				DRM_DEBUG("psp_dbg_drv_version: %u\n",  in amdgpu_ucode_print_psp_hdr()
472 				DRM_DEBUG("psp_dbg_drv_size_bytes: %u\n",  in amdgpu_ucode_print_psp_hdr()
476 				DRM_DEBUG("Unsupported PSP fw type: %d\n", desc->fw_type);  in amdgpu_ucode_print_psp_hdr()
491 	DRM_DEBUG("GPU_INFO\n");  in amdgpu_ucode_print_gpu_info_hdr()
498 		DRM_DEBUG("version_major: %u\n",  in amdgpu_ucode_print_gpu_info_hdr()
500 		DRM_DEBUG("version_minor: %u\n",  in amdgpu_ucode_print_gpu_info_hdr()