Lines Matching refs:adev
37 void amdgpu_gfx_rlc_enter_safe_mode(struct amdgpu_device *adev) in amdgpu_gfx_rlc_enter_safe_mode() argument
39 if (adev->gfx.rlc.in_safe_mode) in amdgpu_gfx_rlc_enter_safe_mode()
43 if (!adev->gfx.rlc.funcs->is_rlc_enabled(adev)) in amdgpu_gfx_rlc_enter_safe_mode()
46 if (adev->cg_flags & in amdgpu_gfx_rlc_enter_safe_mode()
49 adev->gfx.rlc.funcs->set_safe_mode(adev); in amdgpu_gfx_rlc_enter_safe_mode()
50 adev->gfx.rlc.in_safe_mode = true; in amdgpu_gfx_rlc_enter_safe_mode()
61 void amdgpu_gfx_rlc_exit_safe_mode(struct amdgpu_device *adev) in amdgpu_gfx_rlc_exit_safe_mode() argument
63 if (!(adev->gfx.rlc.in_safe_mode)) in amdgpu_gfx_rlc_exit_safe_mode()
67 if (!adev->gfx.rlc.funcs->is_rlc_enabled(adev)) in amdgpu_gfx_rlc_exit_safe_mode()
70 if (adev->cg_flags & in amdgpu_gfx_rlc_exit_safe_mode()
73 adev->gfx.rlc.funcs->unset_safe_mode(adev); in amdgpu_gfx_rlc_exit_safe_mode()
74 adev->gfx.rlc.in_safe_mode = false; in amdgpu_gfx_rlc_exit_safe_mode()
87 int amdgpu_gfx_rlc_init_sr(struct amdgpu_device *adev, u32 dws) in amdgpu_gfx_rlc_init_sr() argument
95 r = amdgpu_bo_create_reserved(adev, dws * 4, PAGE_SIZE, in amdgpu_gfx_rlc_init_sr()
97 &adev->gfx.rlc.save_restore_obj, in amdgpu_gfx_rlc_init_sr()
98 &adev->gfx.rlc.save_restore_gpu_addr, in amdgpu_gfx_rlc_init_sr()
99 (void **)&adev->gfx.rlc.sr_ptr); in amdgpu_gfx_rlc_init_sr()
101 dev_warn(adev->dev, "(%d) create RLC sr bo failed\n", r); in amdgpu_gfx_rlc_init_sr()
102 amdgpu_gfx_rlc_fini(adev); in amdgpu_gfx_rlc_init_sr()
107 src_ptr = adev->gfx.rlc.reg_list; in amdgpu_gfx_rlc_init_sr()
108 dst_ptr = adev->gfx.rlc.sr_ptr; in amdgpu_gfx_rlc_init_sr()
109 for (i = 0; i < adev->gfx.rlc.reg_list_size; i++) in amdgpu_gfx_rlc_init_sr()
111 amdgpu_bo_kunmap(adev->gfx.rlc.save_restore_obj); in amdgpu_gfx_rlc_init_sr()
112 amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj); in amdgpu_gfx_rlc_init_sr()
125 int amdgpu_gfx_rlc_init_csb(struct amdgpu_device *adev) in amdgpu_gfx_rlc_init_csb() argument
131 adev->gfx.rlc.clear_state_size = dws = adev->gfx.rlc.funcs->get_csb_size(adev); in amdgpu_gfx_rlc_init_csb()
132 r = amdgpu_bo_create_kernel(adev, dws * 4, PAGE_SIZE, in amdgpu_gfx_rlc_init_csb()
134 &adev->gfx.rlc.clear_state_obj, in amdgpu_gfx_rlc_init_csb()
135 &adev->gfx.rlc.clear_state_gpu_addr, in amdgpu_gfx_rlc_init_csb()
136 (void **)&adev->gfx.rlc.cs_ptr); in amdgpu_gfx_rlc_init_csb()
138 dev_err(adev->dev, "(%d) failed to create rlc csb bo\n", r); in amdgpu_gfx_rlc_init_csb()
139 amdgpu_gfx_rlc_fini(adev); in amdgpu_gfx_rlc_init_csb()
154 int amdgpu_gfx_rlc_init_cpt(struct amdgpu_device *adev) in amdgpu_gfx_rlc_init_cpt() argument
158 r = amdgpu_bo_create_reserved(adev, adev->gfx.rlc.cp_table_size, in amdgpu_gfx_rlc_init_cpt()
160 &adev->gfx.rlc.cp_table_obj, in amdgpu_gfx_rlc_init_cpt()
161 &adev->gfx.rlc.cp_table_gpu_addr, in amdgpu_gfx_rlc_init_cpt()
162 (void **)&adev->gfx.rlc.cp_table_ptr); in amdgpu_gfx_rlc_init_cpt()
164 dev_err(adev->dev, "(%d) failed to create cp table bo\n", r); in amdgpu_gfx_rlc_init_cpt()
165 amdgpu_gfx_rlc_fini(adev); in amdgpu_gfx_rlc_init_cpt()
170 amdgpu_gfx_rlc_setup_cp_table(adev); in amdgpu_gfx_rlc_init_cpt()
171 amdgpu_bo_kunmap(adev->gfx.rlc.cp_table_obj); in amdgpu_gfx_rlc_init_cpt()
172 amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj); in amdgpu_gfx_rlc_init_cpt()
184 void amdgpu_gfx_rlc_setup_cp_table(struct amdgpu_device *adev) in amdgpu_gfx_rlc_setup_cp_table() argument
192 max_me = adev->gfx.rlc.funcs->get_cp_table_num(adev); in amdgpu_gfx_rlc_setup_cp_table()
195 dst_ptr = adev->gfx.rlc.cp_table_ptr; in amdgpu_gfx_rlc_setup_cp_table()
199 (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; in amdgpu_gfx_rlc_setup_cp_table()
201 (adev->gfx.ce_fw->data + in amdgpu_gfx_rlc_setup_cp_table()
207 (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; in amdgpu_gfx_rlc_setup_cp_table()
209 (adev->gfx.pfp_fw->data + in amdgpu_gfx_rlc_setup_cp_table()
215 (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; in amdgpu_gfx_rlc_setup_cp_table()
217 (adev->gfx.me_fw->data + in amdgpu_gfx_rlc_setup_cp_table()
223 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; in amdgpu_gfx_rlc_setup_cp_table()
225 (adev->gfx.mec_fw->data + in amdgpu_gfx_rlc_setup_cp_table()
231 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data; in amdgpu_gfx_rlc_setup_cp_table()
233 (adev->gfx.mec2_fw->data + in amdgpu_gfx_rlc_setup_cp_table()
256 void amdgpu_gfx_rlc_fini(struct amdgpu_device *adev) in amdgpu_gfx_rlc_fini() argument
259 if (adev->gfx.rlc.save_restore_obj) { in amdgpu_gfx_rlc_fini()
260 amdgpu_bo_free_kernel(&adev->gfx.rlc.save_restore_obj, in amdgpu_gfx_rlc_fini()
261 &adev->gfx.rlc.save_restore_gpu_addr, in amdgpu_gfx_rlc_fini()
262 (void **)&adev->gfx.rlc.sr_ptr); in amdgpu_gfx_rlc_fini()
266 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, in amdgpu_gfx_rlc_fini()
267 &adev->gfx.rlc.clear_state_gpu_addr, in amdgpu_gfx_rlc_fini()
268 (void **)&adev->gfx.rlc.cs_ptr); in amdgpu_gfx_rlc_fini()
271 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, in amdgpu_gfx_rlc_fini()
272 &adev->gfx.rlc.cp_table_gpu_addr, in amdgpu_gfx_rlc_fini()
273 (void **)&adev->gfx.rlc.cp_table_ptr); in amdgpu_gfx_rlc_fini()
276 static int amdgpu_gfx_rlc_init_microcode_v2_0(struct amdgpu_device *adev) in amdgpu_gfx_rlc_init_microcode_v2_0() argument
284 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; in amdgpu_gfx_rlc_init_microcode_v2_0()
286 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version); in amdgpu_gfx_rlc_init_microcode_v2_0()
287 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version); in amdgpu_gfx_rlc_init_microcode_v2_0()
288 adev->gfx.rlc.save_and_restore_offset = in amdgpu_gfx_rlc_init_microcode_v2_0()
290 adev->gfx.rlc.clear_state_descriptor_offset = in amdgpu_gfx_rlc_init_microcode_v2_0()
292 adev->gfx.rlc.avail_scratch_ram_locations = in amdgpu_gfx_rlc_init_microcode_v2_0()
294 adev->gfx.rlc.reg_restore_list_size = in amdgpu_gfx_rlc_init_microcode_v2_0()
296 adev->gfx.rlc.reg_list_format_start = in amdgpu_gfx_rlc_init_microcode_v2_0()
298 adev->gfx.rlc.reg_list_format_separate_start = in amdgpu_gfx_rlc_init_microcode_v2_0()
300 adev->gfx.rlc.starting_offsets_start = in amdgpu_gfx_rlc_init_microcode_v2_0()
302 adev->gfx.rlc.reg_list_format_size_bytes = in amdgpu_gfx_rlc_init_microcode_v2_0()
304 adev->gfx.rlc.reg_list_size_bytes = in amdgpu_gfx_rlc_init_microcode_v2_0()
306 adev->gfx.rlc.register_list_format = in amdgpu_gfx_rlc_init_microcode_v2_0()
307 kmalloc(adev->gfx.rlc.reg_list_format_size_bytes + in amdgpu_gfx_rlc_init_microcode_v2_0()
308 adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL); in amdgpu_gfx_rlc_init_microcode_v2_0()
309 if (!adev->gfx.rlc.register_list_format) { in amdgpu_gfx_rlc_init_microcode_v2_0()
310 dev_err(adev->dev, "failed to allocate memory for rlc register_list_format\n"); in amdgpu_gfx_rlc_init_microcode_v2_0()
317 adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]); in amdgpu_gfx_rlc_init_microcode_v2_0()
319 adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i; in amdgpu_gfx_rlc_init_microcode_v2_0()
324 adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]); in amdgpu_gfx_rlc_init_microcode_v2_0()
326 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { in amdgpu_gfx_rlc_init_microcode_v2_0()
327 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G]; in amdgpu_gfx_rlc_init_microcode_v2_0()
329 info->fw = adev->gfx.rlc_fw; in amdgpu_gfx_rlc_init_microcode_v2_0()
332 adev->firmware.fw_size += in amdgpu_gfx_rlc_init_microcode_v2_0()
340 static void amdgpu_gfx_rlc_init_microcode_v2_1(struct amdgpu_device *adev) in amdgpu_gfx_rlc_init_microcode_v2_1() argument
345 rlc_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data; in amdgpu_gfx_rlc_init_microcode_v2_1()
346 adev->gfx.rlc_srlc_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_ucode_ver); in amdgpu_gfx_rlc_init_microcode_v2_1()
347 adev->gfx.rlc_srlc_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_feature_ver); in amdgpu_gfx_rlc_init_microcode_v2_1()
348 …adev->gfx.rlc.save_restore_list_cntl_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_cntl_size… in amdgpu_gfx_rlc_init_microcode_v2_1()
349 …adev->gfx.rlc.save_restore_list_cntl = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_cntl… in amdgpu_gfx_rlc_init_microcode_v2_1()
350 adev->gfx.rlc_srlg_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_ucode_ver); in amdgpu_gfx_rlc_init_microcode_v2_1()
351 adev->gfx.rlc_srlg_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_feature_ver); in amdgpu_gfx_rlc_init_microcode_v2_1()
352 …adev->gfx.rlc.save_restore_list_gpm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_gpm_size_b… in amdgpu_gfx_rlc_init_microcode_v2_1()
353 …adev->gfx.rlc.save_restore_list_gpm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_gpm_o… in amdgpu_gfx_rlc_init_microcode_v2_1()
354 adev->gfx.rlc_srls_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_ucode_ver); in amdgpu_gfx_rlc_init_microcode_v2_1()
355 adev->gfx.rlc_srls_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_feature_ver); in amdgpu_gfx_rlc_init_microcode_v2_1()
356 …adev->gfx.rlc.save_restore_list_srm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_srm_size_b… in amdgpu_gfx_rlc_init_microcode_v2_1()
357 …adev->gfx.rlc.save_restore_list_srm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_srm_o… in amdgpu_gfx_rlc_init_microcode_v2_1()
358 adev->gfx.rlc.reg_list_format_direct_reg_list_length = in amdgpu_gfx_rlc_init_microcode_v2_1()
361 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { in amdgpu_gfx_rlc_init_microcode_v2_1()
362 if (adev->gfx.rlc.save_restore_list_cntl_size_bytes) { in amdgpu_gfx_rlc_init_microcode_v2_1()
363 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL]; in amdgpu_gfx_rlc_init_microcode_v2_1()
365 info->fw = adev->gfx.rlc_fw; in amdgpu_gfx_rlc_init_microcode_v2_1()
366 adev->firmware.fw_size += in amdgpu_gfx_rlc_init_microcode_v2_1()
367 ALIGN(adev->gfx.rlc.save_restore_list_cntl_size_bytes, PAGE_SIZE); in amdgpu_gfx_rlc_init_microcode_v2_1()
370 if (adev->gfx.rlc.save_restore_list_gpm_size_bytes) { in amdgpu_gfx_rlc_init_microcode_v2_1()
371 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM]; in amdgpu_gfx_rlc_init_microcode_v2_1()
373 info->fw = adev->gfx.rlc_fw; in amdgpu_gfx_rlc_init_microcode_v2_1()
374 adev->firmware.fw_size += in amdgpu_gfx_rlc_init_microcode_v2_1()
375 ALIGN(adev->gfx.rlc.save_restore_list_gpm_size_bytes, PAGE_SIZE); in amdgpu_gfx_rlc_init_microcode_v2_1()
378 if (adev->gfx.rlc.save_restore_list_srm_size_bytes) { in amdgpu_gfx_rlc_init_microcode_v2_1()
379 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM]; in amdgpu_gfx_rlc_init_microcode_v2_1()
381 info->fw = adev->gfx.rlc_fw; in amdgpu_gfx_rlc_init_microcode_v2_1()
382 adev->firmware.fw_size += in amdgpu_gfx_rlc_init_microcode_v2_1()
383 ALIGN(adev->gfx.rlc.save_restore_list_srm_size_bytes, PAGE_SIZE); in amdgpu_gfx_rlc_init_microcode_v2_1()
388 static void amdgpu_gfx_rlc_init_microcode_v2_2(struct amdgpu_device *adev) in amdgpu_gfx_rlc_init_microcode_v2_2() argument
393 rlc_hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data; in amdgpu_gfx_rlc_init_microcode_v2_2()
394 adev->gfx.rlc.rlc_iram_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlc_iram_ucode_size_bytes); in amdgpu_gfx_rlc_init_microcode_v2_2()
395 adev->gfx.rlc.rlc_iram_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlc_iram_ucode_offset_bytes); in amdgpu_gfx_rlc_init_microcode_v2_2()
396 adev->gfx.rlc.rlc_dram_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlc_dram_ucode_size_bytes); in amdgpu_gfx_rlc_init_microcode_v2_2()
397 adev->gfx.rlc.rlc_dram_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlc_dram_ucode_offset_bytes); in amdgpu_gfx_rlc_init_microcode_v2_2()
399 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { in amdgpu_gfx_rlc_init_microcode_v2_2()
400 if (adev->gfx.rlc.rlc_iram_ucode_size_bytes) { in amdgpu_gfx_rlc_init_microcode_v2_2()
401 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_IRAM]; in amdgpu_gfx_rlc_init_microcode_v2_2()
403 info->fw = adev->gfx.rlc_fw; in amdgpu_gfx_rlc_init_microcode_v2_2()
404 adev->firmware.fw_size += in amdgpu_gfx_rlc_init_microcode_v2_2()
405 ALIGN(adev->gfx.rlc.rlc_iram_ucode_size_bytes, PAGE_SIZE); in amdgpu_gfx_rlc_init_microcode_v2_2()
408 if (adev->gfx.rlc.rlc_dram_ucode_size_bytes) { in amdgpu_gfx_rlc_init_microcode_v2_2()
409 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_DRAM]; in amdgpu_gfx_rlc_init_microcode_v2_2()
411 info->fw = adev->gfx.rlc_fw; in amdgpu_gfx_rlc_init_microcode_v2_2()
412 adev->firmware.fw_size += in amdgpu_gfx_rlc_init_microcode_v2_2()
413 ALIGN(adev->gfx.rlc.rlc_dram_ucode_size_bytes, PAGE_SIZE); in amdgpu_gfx_rlc_init_microcode_v2_2()
418 static void amdgpu_gfx_rlc_init_microcode_v2_3(struct amdgpu_device *adev) in amdgpu_gfx_rlc_init_microcode_v2_3() argument
423 rlc_hdr = (const struct rlc_firmware_header_v2_3 *)adev->gfx.rlc_fw->data; in amdgpu_gfx_rlc_init_microcode_v2_3()
424 adev->gfx.rlcp_ucode_version = le32_to_cpu(rlc_hdr->rlcp_ucode_version); in amdgpu_gfx_rlc_init_microcode_v2_3()
425 adev->gfx.rlcp_ucode_feature_version = le32_to_cpu(rlc_hdr->rlcp_ucode_feature_version); in amdgpu_gfx_rlc_init_microcode_v2_3()
426 adev->gfx.rlc.rlcp_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlcp_ucode_size_bytes); in amdgpu_gfx_rlc_init_microcode_v2_3()
427 adev->gfx.rlc.rlcp_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlcp_ucode_offset_bytes); in amdgpu_gfx_rlc_init_microcode_v2_3()
429 adev->gfx.rlcv_ucode_version = le32_to_cpu(rlc_hdr->rlcv_ucode_version); in amdgpu_gfx_rlc_init_microcode_v2_3()
430 adev->gfx.rlcv_ucode_feature_version = le32_to_cpu(rlc_hdr->rlcv_ucode_feature_version); in amdgpu_gfx_rlc_init_microcode_v2_3()
431 adev->gfx.rlc.rlcv_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlcv_ucode_size_bytes); in amdgpu_gfx_rlc_init_microcode_v2_3()
432 adev->gfx.rlc.rlcv_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlcv_ucode_offset_bytes); in amdgpu_gfx_rlc_init_microcode_v2_3()
434 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { in amdgpu_gfx_rlc_init_microcode_v2_3()
435 if (adev->gfx.rlc.rlcp_ucode_size_bytes) { in amdgpu_gfx_rlc_init_microcode_v2_3()
436 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_P]; in amdgpu_gfx_rlc_init_microcode_v2_3()
438 info->fw = adev->gfx.rlc_fw; in amdgpu_gfx_rlc_init_microcode_v2_3()
439 adev->firmware.fw_size += in amdgpu_gfx_rlc_init_microcode_v2_3()
440 ALIGN(adev->gfx.rlc.rlcp_ucode_size_bytes, PAGE_SIZE); in amdgpu_gfx_rlc_init_microcode_v2_3()
443 if (adev->gfx.rlc.rlcv_ucode_size_bytes) { in amdgpu_gfx_rlc_init_microcode_v2_3()
444 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_V]; in amdgpu_gfx_rlc_init_microcode_v2_3()
446 info->fw = adev->gfx.rlc_fw; in amdgpu_gfx_rlc_init_microcode_v2_3()
447 adev->firmware.fw_size += in amdgpu_gfx_rlc_init_microcode_v2_3()
448 ALIGN(adev->gfx.rlc.rlcv_ucode_size_bytes, PAGE_SIZE); in amdgpu_gfx_rlc_init_microcode_v2_3()
453 static void amdgpu_gfx_rlc_init_microcode_v2_4(struct amdgpu_device *adev) in amdgpu_gfx_rlc_init_microcode_v2_4() argument
458 rlc_hdr = (const struct rlc_firmware_header_v2_4 *)adev->gfx.rlc_fw->data; in amdgpu_gfx_rlc_init_microcode_v2_4()
459 …adev->gfx.rlc.global_tap_delays_ucode_size_bytes = le32_to_cpu(rlc_hdr->global_tap_delays_ucode_si… in amdgpu_gfx_rlc_init_microcode_v2_4()
460 …adev->gfx.rlc.global_tap_delays_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->global_tap_delays_uco… in amdgpu_gfx_rlc_init_microcode_v2_4()
461 …adev->gfx.rlc.se0_tap_delays_ucode_size_bytes = le32_to_cpu(rlc_hdr->se0_tap_delays_ucode_size_byt… in amdgpu_gfx_rlc_init_microcode_v2_4()
462 …adev->gfx.rlc.se0_tap_delays_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->se0_tap_delays_ucode_off… in amdgpu_gfx_rlc_init_microcode_v2_4()
463 …adev->gfx.rlc.se1_tap_delays_ucode_size_bytes = le32_to_cpu(rlc_hdr->se1_tap_delays_ucode_size_byt… in amdgpu_gfx_rlc_init_microcode_v2_4()
464 …adev->gfx.rlc.se1_tap_delays_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->se1_tap_delays_ucode_off… in amdgpu_gfx_rlc_init_microcode_v2_4()
465 …adev->gfx.rlc.se2_tap_delays_ucode_size_bytes = le32_to_cpu(rlc_hdr->se2_tap_delays_ucode_size_byt… in amdgpu_gfx_rlc_init_microcode_v2_4()
466 …adev->gfx.rlc.se2_tap_delays_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->se2_tap_delays_ucode_off… in amdgpu_gfx_rlc_init_microcode_v2_4()
467 …adev->gfx.rlc.se3_tap_delays_ucode_size_bytes = le32_to_cpu(rlc_hdr->se3_tap_delays_ucode_size_byt… in amdgpu_gfx_rlc_init_microcode_v2_4()
468 …adev->gfx.rlc.se3_tap_delays_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->se3_tap_delays_ucode_off… in amdgpu_gfx_rlc_init_microcode_v2_4()
470 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { in amdgpu_gfx_rlc_init_microcode_v2_4()
471 if (adev->gfx.rlc.global_tap_delays_ucode_size_bytes) { in amdgpu_gfx_rlc_init_microcode_v2_4()
472 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS]; in amdgpu_gfx_rlc_init_microcode_v2_4()
474 info->fw = adev->gfx.rlc_fw; in amdgpu_gfx_rlc_init_microcode_v2_4()
475 adev->firmware.fw_size += in amdgpu_gfx_rlc_init_microcode_v2_4()
476 ALIGN(adev->gfx.rlc.global_tap_delays_ucode_size_bytes, PAGE_SIZE); in amdgpu_gfx_rlc_init_microcode_v2_4()
479 if (adev->gfx.rlc.se0_tap_delays_ucode_size_bytes) { in amdgpu_gfx_rlc_init_microcode_v2_4()
480 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SE0_TAP_DELAYS]; in amdgpu_gfx_rlc_init_microcode_v2_4()
482 info->fw = adev->gfx.rlc_fw; in amdgpu_gfx_rlc_init_microcode_v2_4()
483 adev->firmware.fw_size += in amdgpu_gfx_rlc_init_microcode_v2_4()
484 ALIGN(adev->gfx.rlc.se0_tap_delays_ucode_size_bytes, PAGE_SIZE); in amdgpu_gfx_rlc_init_microcode_v2_4()
487 if (adev->gfx.rlc.se1_tap_delays_ucode_size_bytes) { in amdgpu_gfx_rlc_init_microcode_v2_4()
488 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SE1_TAP_DELAYS]; in amdgpu_gfx_rlc_init_microcode_v2_4()
490 info->fw = adev->gfx.rlc_fw; in amdgpu_gfx_rlc_init_microcode_v2_4()
491 adev->firmware.fw_size += in amdgpu_gfx_rlc_init_microcode_v2_4()
492 ALIGN(adev->gfx.rlc.se1_tap_delays_ucode_size_bytes, PAGE_SIZE); in amdgpu_gfx_rlc_init_microcode_v2_4()
495 if (adev->gfx.rlc.se2_tap_delays_ucode_size_bytes) { in amdgpu_gfx_rlc_init_microcode_v2_4()
496 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SE2_TAP_DELAYS]; in amdgpu_gfx_rlc_init_microcode_v2_4()
498 info->fw = adev->gfx.rlc_fw; in amdgpu_gfx_rlc_init_microcode_v2_4()
499 adev->firmware.fw_size += in amdgpu_gfx_rlc_init_microcode_v2_4()
500 ALIGN(adev->gfx.rlc.se2_tap_delays_ucode_size_bytes, PAGE_SIZE); in amdgpu_gfx_rlc_init_microcode_v2_4()
503 if (adev->gfx.rlc.se3_tap_delays_ucode_size_bytes) { in amdgpu_gfx_rlc_init_microcode_v2_4()
504 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SE3_TAP_DELAYS]; in amdgpu_gfx_rlc_init_microcode_v2_4()
506 info->fw = adev->gfx.rlc_fw; in amdgpu_gfx_rlc_init_microcode_v2_4()
507 adev->firmware.fw_size += in amdgpu_gfx_rlc_init_microcode_v2_4()
508 ALIGN(adev->gfx.rlc.se3_tap_delays_ucode_size_bytes, PAGE_SIZE); in amdgpu_gfx_rlc_init_microcode_v2_4()
513 int amdgpu_gfx_rlc_init_microcode(struct amdgpu_device *adev, in amdgpu_gfx_rlc_init_microcode() argument
521 dev_err(adev->dev, "unsupported rlc fw hdr\n"); in amdgpu_gfx_rlc_init_microcode()
527 adev->gfx.rlc.is_rlc_v2_1 = true; in amdgpu_gfx_rlc_init_microcode()
530 err = amdgpu_gfx_rlc_init_microcode_v2_0(adev); in amdgpu_gfx_rlc_init_microcode()
532 dev_err(adev->dev, "fail to init rlc v2_0 microcode\n"); in amdgpu_gfx_rlc_init_microcode()
537 amdgpu_gfx_rlc_init_microcode_v2_1(adev); in amdgpu_gfx_rlc_init_microcode()
539 amdgpu_gfx_rlc_init_microcode_v2_2(adev); in amdgpu_gfx_rlc_init_microcode()
541 amdgpu_gfx_rlc_init_microcode_v2_3(adev); in amdgpu_gfx_rlc_init_microcode()
543 amdgpu_gfx_rlc_init_microcode_v2_4(adev); in amdgpu_gfx_rlc_init_microcode()