69  * add to control->i2c_address, and then tell I2C layer to read
100 				       struct amdgpu_ras_eeprom_control *control)  in __get_eeprom_i2c_addr_arct()  argument
104 	if (!control || !atom_ctx)  in __get_eeprom_i2c_addr_arct()
110 		control->i2c_address = EEPROM_I2C_MADDR_ARCTURUS_D342;  in __get_eeprom_i2c_addr_arct()
112 		control->i2c_address = EEPROM_I2C_MADDR_ARCTURUS;  in __get_eeprom_i2c_addr_arct()
118 				  struct amdgpu_ras_eeprom_control *control)  in __get_eeprom_i2c_addr()  argument
122 	if (!control)  in __get_eeprom_i2c_addr()
135 		control->i2c_address = ((u32) i2c_addr) << 16;  in __get_eeprom_i2c_addr()
142 		control->i2c_address = EEPROM_I2C_MADDR_VEGA20;  in __get_eeprom_i2c_addr()
146 		return __get_eeprom_i2c_addr_arct(adev, control);  in __get_eeprom_i2c_addr()
149 		control->i2c_address = EEPROM_I2C_MADDR_SIENNA_CICHLID;  in __get_eeprom_i2c_addr()
153 		control->i2c_address = EEPROM_I2C_MADDR_ALDEBARAN;  in __get_eeprom_i2c_addr()
162 		control->i2c_address = EEPROM_I2C_MADDR_SMU_13_0_0;  in __get_eeprom_i2c_addr()
198 static int __write_table_header(struct amdgpu_ras_eeprom_control *control)  in __write_table_header()  argument
201 	struct amdgpu_device *adev = to_amdgpu_device(control);  in __write_table_header()
205 	__encode_table_header_to_buf(&control->tbl_hdr, buf);  in __write_table_header()
210 				  control->i2c_address +  in __write_table_header()
211 				  control->ras_header_offset,  in __write_table_header()
228 static u8 __calc_hdr_byte_sum(const struct amdgpu_ras_eeprom_control *control)  in __calc_hdr_byte_sum()  argument
235 	sz = sizeof(control->tbl_hdr) - sizeof(control->tbl_hdr.checksum);  in __calc_hdr_byte_sum()
236 	pp = (u8 *) &control->tbl_hdr;  in __calc_hdr_byte_sum()
245 	struct amdgpu_ras_eeprom_control *control,  in amdgpu_ras_eeprom_correct_header_tag()  argument
248 	struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr;  in amdgpu_ras_eeprom_correct_header_tag()
260 	mutex_lock(&control->ras_tbl_mutex);  in amdgpu_ras_eeprom_correct_header_tag()
263 	res = __write_table_header(control);  in amdgpu_ras_eeprom_correct_header_tag()
264 	mutex_unlock(&control->ras_tbl_mutex);  in amdgpu_ras_eeprom_correct_header_tag()
271  * @control: pointer to control structure
276 int amdgpu_ras_eeprom_reset_table(struct amdgpu_ras_eeprom_control *control)  in amdgpu_ras_eeprom_reset_table()  argument
278 	struct amdgpu_device *adev = to_amdgpu_device(control);  in amdgpu_ras_eeprom_reset_table()
279 	struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr;  in amdgpu_ras_eeprom_reset_table()
284 	mutex_lock(&control->ras_tbl_mutex);  in amdgpu_ras_eeprom_reset_table()
291 	csum = __calc_hdr_byte_sum(control);  in amdgpu_ras_eeprom_reset_table()
294 	res = __write_table_header(control);  in amdgpu_ras_eeprom_reset_table()
296 	control->ras_num_recs = 0;  in amdgpu_ras_eeprom_reset_table()
297 	control->ras_fri = 0;  in amdgpu_ras_eeprom_reset_table()
299 	amdgpu_dpm_send_hbm_bad_pages_num(adev, control->ras_num_recs);  in amdgpu_ras_eeprom_reset_table()
301 	control->bad_channel_bitmap = 0;  in amdgpu_ras_eeprom_reset_table()
302 	amdgpu_dpm_send_hbm_bad_channel_flag(adev, control->bad_channel_bitmap);  in amdgpu_ras_eeprom_reset_table()
305 	amdgpu_ras_debugfs_set_ret_size(control);  in amdgpu_ras_eeprom_reset_table()
307 	mutex_unlock(&control->ras_tbl_mutex);  in amdgpu_ras_eeprom_reset_table()
313 __encode_table_record_to_buf(struct amdgpu_ras_eeprom_control *control,  in __encode_table_record_to_buf()  argument
341 __decode_table_record_from_buf(struct amdgpu_ras_eeprom_control *control,  in __decode_table_record_from_buf()  argument
394  * @control: pointer to control structure
399  * The caller must hold the table mutex in @control.
402 static int __amdgpu_ras_eeprom_write(struct amdgpu_ras_eeprom_control *control,  in __amdgpu_ras_eeprom_write()  argument
405 	struct amdgpu_device *adev = to_amdgpu_device(control);  in __amdgpu_ras_eeprom_write()
413 				  control->i2c_address +  in __amdgpu_ras_eeprom_write()
414 				  RAS_INDEX_TO_OFFSET(control, fri),  in __amdgpu_ras_eeprom_write()
434 amdgpu_ras_eeprom_append_table(struct amdgpu_ras_eeprom_control *control,  in amdgpu_ras_eeprom_append_table()  argument
438 	struct amdgpu_ras *con = amdgpu_ras_get_context(to_amdgpu_device(control));  in amdgpu_ras_eeprom_append_table()
451 		__encode_table_record_to_buf(control, &record[i], pp);  in amdgpu_ras_eeprom_append_table()
454 		if (!(control->bad_channel_bitmap & (1 << record[i].mem_channel))) {  in amdgpu_ras_eeprom_append_table()
455 			control->bad_channel_bitmap |= 1 << record[i].mem_channel;  in amdgpu_ras_eeprom_append_table()
464 	 * Let N = control->ras_max_num_record_count, then we have,  in amdgpu_ras_eeprom_append_table()
487 	a = control->ras_fri + control->ras_num_recs;  in amdgpu_ras_eeprom_append_table()
489 	if (b < control->ras_max_record_count) {  in amdgpu_ras_eeprom_append_table()
490 		res = __amdgpu_ras_eeprom_write(control, buf, a, num);  in amdgpu_ras_eeprom_append_table()
491 	} else if (a < control->ras_max_record_count) {  in amdgpu_ras_eeprom_append_table()
494 		g0 = control->ras_max_record_count - a;  in amdgpu_ras_eeprom_append_table()
495 		g1 = b % control->ras_max_record_count + 1;  in amdgpu_ras_eeprom_append_table()
496 		res = __amdgpu_ras_eeprom_write(control, buf, a, g0);  in amdgpu_ras_eeprom_append_table()
499 		res = __amdgpu_ras_eeprom_write(control,  in amdgpu_ras_eeprom_append_table()
504 		if (g1 > control->ras_fri)  in amdgpu_ras_eeprom_append_table()
505 			control->ras_fri = g1 % control->ras_max_record_count;  in amdgpu_ras_eeprom_append_table()
507 		a %= control->ras_max_record_count;  in amdgpu_ras_eeprom_append_table()
508 		b %= control->ras_max_record_count;  in amdgpu_ras_eeprom_append_table()
512 			res = __amdgpu_ras_eeprom_write(control, buf, a, num);  in amdgpu_ras_eeprom_append_table()
515 			if (b >= control->ras_fri)  in amdgpu_ras_eeprom_append_table()
516 				control->ras_fri = (b + 1) % control->ras_max_record_count;  in amdgpu_ras_eeprom_append_table()
524 			g0 = control->ras_max_record_count - a;  in amdgpu_ras_eeprom_append_table()
526 			res = __amdgpu_ras_eeprom_write(control, buf, a, g0);  in amdgpu_ras_eeprom_append_table()
529 			res = __amdgpu_ras_eeprom_write(control,  in amdgpu_ras_eeprom_append_table()
534 			control->ras_fri = g1 % control->ras_max_record_count;  in amdgpu_ras_eeprom_append_table()
537 	control->ras_num_recs = 1 + (control->ras_max_record_count + b  in amdgpu_ras_eeprom_append_table()
538 				     - control->ras_fri)  in amdgpu_ras_eeprom_append_table()
539 		% control->ras_max_record_count;  in amdgpu_ras_eeprom_append_table()
546 amdgpu_ras_eeprom_update_header(struct amdgpu_ras_eeprom_control *control)  in amdgpu_ras_eeprom_update_header()  argument
548 	struct amdgpu_device *adev = to_amdgpu_device(control);  in amdgpu_ras_eeprom_update_header()
557 	    control->ras_num_recs >= ras->bad_page_cnt_threshold) {  in amdgpu_ras_eeprom_update_header()
560 			control->ras_num_recs, ras->bad_page_cnt_threshold);  in amdgpu_ras_eeprom_update_header()
561 		control->tbl_hdr.header = RAS_TABLE_HDR_BAD;  in amdgpu_ras_eeprom_update_header()
564 	control->tbl_hdr.version = RAS_TABLE_VER;  in amdgpu_ras_eeprom_update_header()
565 	control->tbl_hdr.first_rec_offset = RAS_INDEX_TO_OFFSET(control, control->ras_fri);  in amdgpu_ras_eeprom_update_header()
566 	control->tbl_hdr.tbl_size = RAS_TABLE_HEADER_SIZE + control->ras_num_recs * RAS_TABLE_RECORD_SIZE;  in amdgpu_ras_eeprom_update_header()
567 	control->tbl_hdr.checksum = 0;  in amdgpu_ras_eeprom_update_header()
569 	buf_size = control->ras_num_recs * RAS_TABLE_RECORD_SIZE;  in amdgpu_ras_eeprom_update_header()
570 	buf = kcalloc(control->ras_num_recs, RAS_TABLE_RECORD_SIZE, GFP_KERNEL);  in amdgpu_ras_eeprom_update_header()
573 			  control->tbl_hdr.tbl_size);  in amdgpu_ras_eeprom_update_header()
580 				 control->i2c_address +  in amdgpu_ras_eeprom_update_header()
581 				 control->ras_record_offset,  in amdgpu_ras_eeprom_update_header()
601 	csum += __calc_hdr_byte_sum(control);  in amdgpu_ras_eeprom_update_header()
604 	control->tbl_hdr.checksum = csum;  in amdgpu_ras_eeprom_update_header()
605 	res = __write_table_header(control);  in amdgpu_ras_eeprom_update_header()
613  * @control: pointer to control structure
619  * can be appended is between 1 and control->ras_max_record_count,
624 int amdgpu_ras_eeprom_append(struct amdgpu_ras_eeprom_control *control,  in amdgpu_ras_eeprom_append()  argument
628 	struct amdgpu_device *adev = to_amdgpu_device(control);  in amdgpu_ras_eeprom_append()
637 	} else if (num > control->ras_max_record_count) {  in amdgpu_ras_eeprom_append()
639 			  num, control->ras_max_record_count);  in amdgpu_ras_eeprom_append()
643 	mutex_lock(&control->ras_tbl_mutex);  in amdgpu_ras_eeprom_append()
645 	res = amdgpu_ras_eeprom_append_table(control, record, num);  in amdgpu_ras_eeprom_append()
647 		res = amdgpu_ras_eeprom_update_header(control);  in amdgpu_ras_eeprom_append()
649 		amdgpu_ras_debugfs_set_ret_size(control);  in amdgpu_ras_eeprom_append()
651 	mutex_unlock(&control->ras_tbl_mutex);  in amdgpu_ras_eeprom_append()
657  * @control: pointer to control structure
662  * The caller must hold the table mutex in @control.
665 static int __amdgpu_ras_eeprom_read(struct amdgpu_ras_eeprom_control *control,  in __amdgpu_ras_eeprom_read()  argument
668 	struct amdgpu_device *adev = to_amdgpu_device(control);  in __amdgpu_ras_eeprom_read()
676 				 control->i2c_address +  in __amdgpu_ras_eeprom_read()
677 				 RAS_INDEX_TO_OFFSET(control, fri),  in __amdgpu_ras_eeprom_read()
698  * @control: pointer to control structure
707 int amdgpu_ras_eeprom_read(struct amdgpu_ras_eeprom_control *control,  in amdgpu_ras_eeprom_read()  argument
711 	struct amdgpu_device *adev = to_amdgpu_device(control);  in amdgpu_ras_eeprom_read()
723 	} else if (num > control->ras_num_recs) {  in amdgpu_ras_eeprom_read()
725 			  num, control->ras_num_recs);  in amdgpu_ras_eeprom_read()
753 	g0 = control->ras_fri + num - 1;  in amdgpu_ras_eeprom_read()
754 	g1 = g0 % control->ras_max_record_count;  in amdgpu_ras_eeprom_read()
755 	if (g0 < control->ras_max_record_count) {  in amdgpu_ras_eeprom_read()
759 		g0 = control->ras_max_record_count - control->ras_fri;  in amdgpu_ras_eeprom_read()
763 	mutex_lock(&control->ras_tbl_mutex);  in amdgpu_ras_eeprom_read()
764 	res = __amdgpu_ras_eeprom_read(control, buf, control->ras_fri, g0);  in amdgpu_ras_eeprom_read()
768 		res = __amdgpu_ras_eeprom_read(control,  in amdgpu_ras_eeprom_read()
781 		__decode_table_record_from_buf(control, &record[i], pp);  in amdgpu_ras_eeprom_read()
784 		if (!(control->bad_channel_bitmap & (1 << record[i].mem_channel))) {  in amdgpu_ras_eeprom_read()
785 			control->bad_channel_bitmap |= 1 << record[i].mem_channel;  in amdgpu_ras_eeprom_read()
791 	mutex_unlock(&control->ras_tbl_mutex);  in amdgpu_ras_eeprom_read()
807 	struct amdgpu_ras_eeprom_control *control = ras ? &ras->eeprom_control : NULL;  in amdgpu_ras_debugfs_eeprom_size_read()  local
814 	if (!ras || !control) {  in amdgpu_ras_debugfs_eeprom_size_read()
818 			       RAS_TBL_SIZE_BYTES, control->ras_max_record_count);  in amdgpu_ras_debugfs_eeprom_size_read()
855 static loff_t amdgpu_ras_debugfs_table_size(struct amdgpu_ras_eeprom_control *control)  in amdgpu_ras_debugfs_table_size()  argument
858 		strlen(rec_hdr_str) + rec_hdr_fmt_size * control->ras_num_recs;  in amdgpu_ras_debugfs_table_size()
861 void amdgpu_ras_debugfs_set_ret_size(struct amdgpu_ras_eeprom_control *control)  in amdgpu_ras_debugfs_set_ret_size()  argument
863 	struct amdgpu_ras *ras = container_of(control, struct amdgpu_ras,  in amdgpu_ras_debugfs_set_ret_size()
868 		d_inode(de)->i_size = amdgpu_ras_debugfs_table_size(control);  in amdgpu_ras_debugfs_set_ret_size()
876 	struct amdgpu_ras_eeprom_control *control = &ras->eeprom_control;  in amdgpu_ras_debugfs_table_read()  local
881 	mutex_lock(&control->ras_tbl_mutex);  in amdgpu_ras_debugfs_table_read()
903 			 control->tbl_hdr.header,  in amdgpu_ras_debugfs_table_read()
904 			 control->tbl_hdr.version,  in amdgpu_ras_debugfs_table_read()
905 			 control->tbl_hdr.first_rec_offset,  in amdgpu_ras_debugfs_table_read()
906 			 control->tbl_hdr.tbl_size,  in amdgpu_ras_debugfs_table_read()
907 			 control->tbl_hdr.checksum);  in amdgpu_ras_debugfs_table_read()
933 	data_len = amdgpu_ras_debugfs_table_size(control);  in amdgpu_ras_debugfs_table_read()
949 		for ( ; size > 0 && s < control->ras_num_recs; s++) {  in amdgpu_ras_debugfs_table_read()
950 			u32 ai = RAS_RI_TO_AI(control, s);  in amdgpu_ras_debugfs_table_read()
953 			res = __amdgpu_ras_eeprom_read(control, dare, ai, 1);  in amdgpu_ras_debugfs_table_read()
956 			__decode_table_record_from_buf(control, &record, dare);  in amdgpu_ras_debugfs_table_read()
959 				 RAS_INDEX_TO_OFFSET(control, ai),  in amdgpu_ras_debugfs_table_read()
981 	mutex_unlock(&control->ras_tbl_mutex);  in amdgpu_ras_debugfs_table_read()
991 	struct amdgpu_ras_eeprom_control *control = ras ? &ras->eeprom_control : NULL;  in amdgpu_ras_debugfs_eeprom_table_read()  local
998 	if (!ras || !control) {  in amdgpu_ras_debugfs_eeprom_table_read()
1026  * @control: pointer to control structure
1034 static int __verify_ras_table_checksum(struct amdgpu_ras_eeprom_control *control)  in __verify_ras_table_checksum()  argument
1036 	struct amdgpu_device *adev = to_amdgpu_device(control);  in __verify_ras_table_checksum()
1041 		control->ras_num_recs * RAS_TABLE_RECORD_SIZE;  in __verify_ras_table_checksum()
1049 				 control->i2c_address +  in __verify_ras_table_checksum()
1050 				 control->ras_header_offset,  in __verify_ras_table_checksum()
1069 int amdgpu_ras_eeprom_init(struct amdgpu_ras_eeprom_control *control,  in amdgpu_ras_eeprom_init()  argument
1072 	struct amdgpu_device *adev = to_amdgpu_device(control);  in amdgpu_ras_eeprom_init()
1074 	struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr;  in amdgpu_ras_eeprom_init()
1087 	if (!__get_eeprom_i2c_addr(adev, control))  in amdgpu_ras_eeprom_init()
1090 	control->ras_header_offset = RAS_HDR_START;  in amdgpu_ras_eeprom_init()
1091 	control->ras_record_offset = RAS_RECORD_START;  in amdgpu_ras_eeprom_init()
1092 	control->ras_max_record_count  = RAS_MAX_RECORD_COUNT;  in amdgpu_ras_eeprom_init()
1093 	mutex_init(&control->ras_tbl_mutex);  in amdgpu_ras_eeprom_init()
1097 				 control->i2c_address + control->ras_header_offset,  in amdgpu_ras_eeprom_init()
1106 	control->ras_num_recs = RAS_NUM_RECS(hdr);  in amdgpu_ras_eeprom_init()
1107 	control->ras_fri = RAS_OFFSET_TO_INDEX(control, hdr->first_rec_offset);  in amdgpu_ras_eeprom_init()
1111 				 control->ras_num_recs);  in amdgpu_ras_eeprom_init()
1112 		res = __verify_ras_table_checksum(control);  in amdgpu_ras_eeprom_init()
1119 		if (10 * control->ras_num_recs >= 9 * ras->bad_page_cnt_threshold)  in amdgpu_ras_eeprom_init()
1121 					control->ras_num_recs,  in amdgpu_ras_eeprom_init()
1125 		res = __verify_ras_table_checksum(control);  in amdgpu_ras_eeprom_init()
1129 		if (ras->bad_page_cnt_threshold > control->ras_num_recs) {  in amdgpu_ras_eeprom_init()
1132 			 * ras->bad_page_cnt_threshold - control->num_recs > 0,  in amdgpu_ras_eeprom_init()
1139 				 control->ras_num_recs,  in amdgpu_ras_eeprom_init()
1141 			res = amdgpu_ras_eeprom_correct_header_tag(control,  in amdgpu_ras_eeprom_init()
1145 				control->ras_num_recs, ras->bad_page_cnt_threshold);  in amdgpu_ras_eeprom_init()
1154 					control->ras_num_recs, ras->bad_page_cnt_threshold);  in amdgpu_ras_eeprom_init()
1160 		res = amdgpu_ras_eeprom_reset_table(control);  in amdgpu_ras_eeprom_init()