94 	if (ras_block->block >= AMDGPU_RAS_BLOCK_COUNT)  in get_ras_block_str()
97 	if (ras_block->block == AMDGPU_RAS_BLOCK__MCA)  in get_ras_block_str()
98 		return ras_mca_block_string[ras_block->sub_block_index];  in get_ras_block_str()
100 	return ras_block_string[ras_block->block];  in get_ras_block_str()
140 		amdgpu_ras_get_context(adev)->error_query_ready = ready;  in amdgpu_ras_set_error_query_ready()
146 		return amdgpu_ras_get_context(adev)->error_query_ready;  in amdgpu_ras_get_error_query_ready()
156 	if ((address >= adev->gmc.mc_vram_size) ||  in amdgpu_reserve_page_direct()
158 		dev_warn(adev->dev,  in amdgpu_reserve_page_direct()
159 		         "RAS WARN: input address 0x%llx is invalid.\n",  in amdgpu_reserve_page_direct()
161 		return -EINVAL;  in amdgpu_reserve_page_direct()
165 		dev_warn(adev->dev,  in amdgpu_reserve_page_direct()
182 	dev_warn(adev->dev, "WARNING: THIS IS ONLY FOR TEST PURPOSES AND WILL CORRUPT RAS EEPROM\n");  in amdgpu_reserve_page_direct()
183 	dev_warn(adev->dev, "Clear EEPROM:\n");  in amdgpu_reserve_page_direct()
184 	dev_warn(adev->dev, "    echo 1 > /sys/kernel/debug/dri/0/ras/ras_eeprom_reset\n");  in amdgpu_reserve_page_direct()
192 	struct ras_manager *obj = (struct ras_manager *)file_inode(f)->i_private;  in amdgpu_ras_debugfs_read()
194 		.head = obj->head,  in amdgpu_ras_debugfs_read()
199 	if (amdgpu_ras_query_error_status(obj->adev, &info))  in amdgpu_ras_debugfs_read()
200 		return -EINVAL;  in amdgpu_ras_debugfs_read()
203 	if (obj->adev->ip_versions[MP0_HWIP][0] != IP_VERSION(11, 0, 2) &&  in amdgpu_ras_debugfs_read()
204 	    obj->adev->ip_versions[MP0_HWIP][0] != IP_VERSION(11, 0, 4)) {  in amdgpu_ras_debugfs_read()
205 		if (amdgpu_ras_reset_error_status(obj->adev, info.head.block))  in amdgpu_ras_debugfs_read()
206 			dev_warn(obj->adev->dev, "Failed to reset error counter and error status");  in amdgpu_ras_debugfs_read()
215 	s -= *pos;  in amdgpu_ras_debugfs_read()
220 		return -EINVAL;  in amdgpu_ras_debugfs_read()
243 	return -EINVAL;  in amdgpu_ras_find_block_id_by_name()
254 	int op = -1;  in amdgpu_ras_debugfs_ctrl_parse_data()
260 		return -EINVAL;  in amdgpu_ras_debugfs_ctrl_parse_data()
267 		return -EINVAL;  in amdgpu_ras_debugfs_ctrl_parse_data()
279 		return -EINVAL;  in amdgpu_ras_debugfs_ctrl_parse_data()
281 	if (op != -1) {  in amdgpu_ras_debugfs_ctrl_parse_data()
285 				return -EINVAL;  in amdgpu_ras_debugfs_ctrl_parse_data()
287 			data->op = op;  in amdgpu_ras_debugfs_ctrl_parse_data()
288 			data->inject.address = address;  in amdgpu_ras_debugfs_ctrl_parse_data()
294 			return -EINVAL;  in amdgpu_ras_debugfs_ctrl_parse_data()
296 		data->head.block = block_id;  in amdgpu_ras_debugfs_ctrl_parse_data()
299 			data->head.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;  in amdgpu_ras_debugfs_ctrl_parse_data()
301 			data->head.type = AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE;  in amdgpu_ras_debugfs_ctrl_parse_data()
303 			return -EINVAL;  in amdgpu_ras_debugfs_ctrl_parse_data()
305 		data->op = op;  in amdgpu_ras_debugfs_ctrl_parse_data()
312 				return -EINVAL;  in amdgpu_ras_debugfs_ctrl_parse_data()
313 			data->head.sub_block_index = sub_block;  in amdgpu_ras_debugfs_ctrl_parse_data()
314 			data->inject.address = address;  in amdgpu_ras_debugfs_ctrl_parse_data()
315 			data->inject.value = value;  in amdgpu_ras_debugfs_ctrl_parse_data()
319 			return -EINVAL;  in amdgpu_ras_debugfs_ctrl_parse_data()
322 			return -EINVAL;  in amdgpu_ras_debugfs_ctrl_parse_data()
350  * - 0: disable RAS on the block. Take ::head as its data.
351  * - 1: enable RAS on the block. Take ::head as its data.
352  * - 2: inject errors on the block. Take ::inject as its data.
363  * .. code-block:: bash
367 …*	echo "inject  <block> <error> <sub-block> <address> <value> > /sys/kernel/debug/dri/<N>/ras/ras_…
379  *	ue is multi-uncorrectable
380  *	ce is single-correctable
382  * The sub-block is a the sub-block index, pass 0 if there is no sub-block.
387  * .. code-block:: bash
411 	struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private;  in amdgpu_ras_debugfs_ctrl_write()
416 		dev_warn(adev->dev, "RAS WARN: error injection "  in amdgpu_ras_debugfs_ctrl_write()
434 		return -EINVAL;  in amdgpu_ras_debugfs_ctrl_write()
444 		if ((data.inject.address >= adev->gmc.mc_vram_size) ||  in amdgpu_ras_debugfs_ctrl_write()
446 			dev_warn(adev->dev, "RAS WARN: input address "  in amdgpu_ras_debugfs_ctrl_write()
449 			ret = -EINVAL;  in amdgpu_ras_debugfs_ctrl_write()
456 			dev_warn(adev->dev, "RAS WARN: inject: 0x%llx has "  in amdgpu_ras_debugfs_ctrl_write()
466 		ret = -EINVAL;  in amdgpu_ras_debugfs_ctrl_write()
485  * .. code-block:: bash
497 		(struct amdgpu_device *)file_inode(f)->i_private;  in amdgpu_ras_debugfs_eeprom_write()
501 		&(amdgpu_ras_get_context(adev)->eeprom_control));  in amdgpu_ras_debugfs_eeprom_write()
506 		amdgpu_ras_get_context(adev)->flags = RAS_DEFAULT_FLAGS;  in amdgpu_ras_debugfs_eeprom_write()
542  * .. code-block:: bash
553 		.head = obj->head,  in amdgpu_ras_sysfs_read()
556 	if (!amdgpu_ras_get_error_query_ready(obj->adev))  in amdgpu_ras_sysfs_read()
559 	if (amdgpu_ras_query_error_status(obj->adev, &info))  in amdgpu_ras_sysfs_read()
560 		return -EINVAL;  in amdgpu_ras_sysfs_read()
562 	if (obj->adev->ip_versions[MP0_HWIP][0] != IP_VERSION(11, 0, 2) &&  in amdgpu_ras_sysfs_read()
563 	    obj->adev->ip_versions[MP0_HWIP][0] != IP_VERSION(11, 0, 4)) {  in amdgpu_ras_sysfs_read()
564 		if (amdgpu_ras_reset_error_status(obj->adev, info.head.block))  in amdgpu_ras_sysfs_read()
565 			dev_warn(obj->adev->dev, "Failed to reset error counter and error status");  in amdgpu_ras_sysfs_read()
574 #define get_obj(obj) do { (obj)->use++; } while (0)
575 #define alive_obj(obj) ((obj)->use)
579 	if (obj && (--obj->use == 0))  in put_obj()
580 		list_del(&obj->node);  in put_obj()
581 	if (obj && (obj->use < 0))  in put_obj()
582 		DRM_ERROR("RAS ERROR: Unbalance obj(%s) use\n", get_ras_block_str(&obj->head));  in put_obj()
592 	if (!adev->ras_enabled || !con)  in amdgpu_ras_create_obj()
595 	if (head->block >= AMDGPU_RAS_BLOCK_COUNT)  in amdgpu_ras_create_obj()
598 	if (head->block == AMDGPU_RAS_BLOCK__MCA) {  in amdgpu_ras_create_obj()
599 		if (head->sub_block_index >= AMDGPU_RAS_MCA_BLOCK__LAST)  in amdgpu_ras_create_obj()
602 		obj = &con->objs[AMDGPU_RAS_BLOCK__LAST + head->sub_block_index];  in amdgpu_ras_create_obj()
604 		obj = &con->objs[head->block];  in amdgpu_ras_create_obj()
610 	obj->head = *head;  in amdgpu_ras_create_obj()
611 	obj->adev = adev;  in amdgpu_ras_create_obj()
612 	list_add(&obj->node, &con->head);  in amdgpu_ras_create_obj()
626 	if (!adev->ras_enabled || !con)  in amdgpu_ras_find_obj()
630 		if (head->block >= AMDGPU_RAS_BLOCK_COUNT)  in amdgpu_ras_find_obj()
633 		if (head->block == AMDGPU_RAS_BLOCK__MCA) {  in amdgpu_ras_find_obj()
634 			if (head->sub_block_index >= AMDGPU_RAS_MCA_BLOCK__LAST)  in amdgpu_ras_find_obj()
637 			obj = &con->objs[AMDGPU_RAS_BLOCK__LAST + head->sub_block_index];  in amdgpu_ras_find_obj()
639 			obj = &con->objs[head->block];  in amdgpu_ras_find_obj()
645 			obj = &con->objs[i];  in amdgpu_ras_find_obj()
659 	return adev->ras_hw_enabled & BIT(head->block);  in amdgpu_ras_is_feature_allowed()
667 	return con->features & BIT(head->block);  in amdgpu_ras_is_feature_enabled()
682 	 * Ras framework checks con->hw_supported to see if it need do  in __amdgpu_ras_feature_enable()
684 	 * IP checks con->support to see if it need disable ras.  in __amdgpu_ras_feature_enable()
693 				return -EINVAL;  in __amdgpu_ras_feature_enable()
698 		con->features |= BIT(head->block);  in __amdgpu_ras_feature_enable()
701 			con->features &= ~BIT(head->block);  in __amdgpu_ras_feature_enable()
718 		return -EINVAL;  in amdgpu_ras_feature_enable()
720 	if (head->block == AMDGPU_RAS_BLOCK__GFX) {  in amdgpu_ras_feature_enable()
723 			return -ENOMEM;  in amdgpu_ras_feature_enable()
726 			info->disable_features = (struct ta_ras_disable_features_input) {  in amdgpu_ras_feature_enable()
727 				.block_id =  amdgpu_ras_block_to_ta(head->block),  in amdgpu_ras_feature_enable()
728 				.error_type = amdgpu_ras_error_to_ta(head->type),  in amdgpu_ras_feature_enable()
731 			info->enable_features = (struct ta_ras_enable_features_input) {  in amdgpu_ras_feature_enable()
732 				.block_id =  amdgpu_ras_block_to_ta(head->block),  in amdgpu_ras_feature_enable()
733 				.error_type = amdgpu_ras_error_to_ta(head->type),  in amdgpu_ras_feature_enable()
742 	if (head->block == AMDGPU_RAS_BLOCK__GFX &&  in amdgpu_ras_feature_enable()
745 		ret = psp_ras_enable_features(&adev->psp, info, enable);  in amdgpu_ras_feature_enable()
747 			dev_err(adev->dev, "ras %s %s failed poison:%d ret:%d\n",  in amdgpu_ras_feature_enable()
759 	if (head->block == AMDGPU_RAS_BLOCK__GFX)  in amdgpu_ras_feature_enable()
772 		return -EINVAL;  in amdgpu_ras_feature_enable_on_boot()
774 	if (con->flags & AMDGPU_RAS_FLAG_INIT_BY_VBIOS) {  in amdgpu_ras_feature_enable_on_boot()
780 			 * with error code -EAGAIN.  in amdgpu_ras_feature_enable_on_boot()
787 			if (ret == -EINVAL) {  in amdgpu_ras_feature_enable_on_boot()
790 					dev_info(adev->dev,  in amdgpu_ras_feature_enable_on_boot()
800 			/* gfx block ras dsiable cmd must send to ras-ta */  in amdgpu_ras_feature_enable_on_boot()
801 			if (head->block == AMDGPU_RAS_BLOCK__GFX)  in amdgpu_ras_feature_enable_on_boot()
802 				con->features |= BIT(head->block);  in amdgpu_ras_feature_enable_on_boot()
807 			if (adev->ras_enabled && head->block == AMDGPU_RAS_BLOCK__GFX)  in amdgpu_ras_feature_enable_on_boot()
808 				con->features &= ~BIT(head->block);  in amdgpu_ras_feature_enable_on_boot()
822 	list_for_each_entry_safe(obj, tmp, &con->head, node) {  in amdgpu_ras_disable_all_features()
827 			if (__amdgpu_ras_feature_enable(adev, &obj->head, 0))  in amdgpu_ras_disable_all_features()
830 			if (amdgpu_ras_feature_enable(adev, &obj->head, 0))  in amdgpu_ras_disable_all_features()
835 	return con->features;  in amdgpu_ras_disable_all_features()
888 	return con->features;  in amdgpu_ras_enable_all_features()
896 		return -EINVAL;  in amdgpu_ras_block_match_default()
898 	if (block_obj->ras_comm.block == block)  in amdgpu_ras_block_match_default()
901 	return -EINVAL;  in amdgpu_ras_block_match_default()
916 	list_for_each_entry_safe(node, tmp, &adev->ras_list, node) {  in amdgpu_ras_get_ras_block()
917 		if (!node->ras_obj) {  in amdgpu_ras_get_ras_block()
918 			dev_warn(adev->dev, "Warning: abnormal ras list node.\n");  in amdgpu_ras_get_ras_block()
922 		obj = node->ras_obj;  in amdgpu_ras_get_ras_block()
923 		if (obj->ras_block_match) {  in amdgpu_ras_get_ras_block()
924 			if (obj->ras_block_match(obj, block, sub_block_index) == 0)  in amdgpu_ras_get_ras_block()
944 	ret = amdgpu_dpm_get_ecc_info(adev, (void *)&(ras->umc_ecc));  in amdgpu_ras_get_ecc_info()
945 	if (ret == -EOPNOTSUPP) {  in amdgpu_ras_get_ecc_info()
946 		if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops &&  in amdgpu_ras_get_ecc_info()
947 			adev->umc.ras->ras_block.hw_ops->query_ras_error_count)  in amdgpu_ras_get_ecc_info()
948 			adev->umc.ras->ras_block.hw_ops->query_ras_error_count(adev, err_data);  in amdgpu_ras_get_ecc_info()
953 		if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops &&  in amdgpu_ras_get_ecc_info()
954 		    adev->umc.ras->ras_block.hw_ops->query_ras_error_address)  in amdgpu_ras_get_ecc_info()
955 			adev->umc.ras->ras_block.hw_ops->query_ras_error_address(adev, err_data);  in amdgpu_ras_get_ecc_info()
957 		if (adev->umc.ras &&  in amdgpu_ras_get_ecc_info()
958 			adev->umc.ras->ecc_info_query_ras_error_count)  in amdgpu_ras_get_ecc_info()
959 			adev->umc.ras->ecc_info_query_ras_error_count(adev, err_data);  in amdgpu_ras_get_ecc_info()
961 		if (adev->umc.ras &&  in amdgpu_ras_get_ecc_info()
962 			adev->umc.ras->ecc_info_query_ras_error_address)  in amdgpu_ras_get_ecc_info()
963 			adev->umc.ras->ecc_info_query_ras_error_address(adev, err_data);  in amdgpu_ras_get_ecc_info()
972 	struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);  in amdgpu_ras_query_error_status()
976 		return -EINVAL;  in amdgpu_ras_query_error_status()
978 	if (info->head.block == AMDGPU_RAS_BLOCK__UMC) {  in amdgpu_ras_query_error_status()
981 		block_obj = amdgpu_ras_get_ras_block(adev, info->head.block, 0);  in amdgpu_ras_query_error_status()
982 		if (!block_obj || !block_obj->hw_ops)   {  in amdgpu_ras_query_error_status()
983 			dev_dbg_once(adev->dev, "%s doesn't config RAS function\n",  in amdgpu_ras_query_error_status()
984 				     get_ras_block_str(&info->head));  in amdgpu_ras_query_error_status()
985 			return -EINVAL;  in amdgpu_ras_query_error_status()
988 		if (block_obj->hw_ops->query_ras_error_count)  in amdgpu_ras_query_error_status()
989 			block_obj->hw_ops->query_ras_error_count(adev, &err_data);  in amdgpu_ras_query_error_status()
991 		if ((info->head.block == AMDGPU_RAS_BLOCK__SDMA) ||  in amdgpu_ras_query_error_status()
992 		    (info->head.block == AMDGPU_RAS_BLOCK__GFX) ||  in amdgpu_ras_query_error_status()
993 		    (info->head.block == AMDGPU_RAS_BLOCK__MMHUB)) {  in amdgpu_ras_query_error_status()
994 				if (block_obj->hw_ops->query_ras_error_status)  in amdgpu_ras_query_error_status()
995 					block_obj->hw_ops->query_ras_error_status(adev);  in amdgpu_ras_query_error_status()
999 	obj->err_data.ue_count += err_data.ue_count;  in amdgpu_ras_query_error_status()
1000 	obj->err_data.ce_count += err_data.ce_count;  in amdgpu_ras_query_error_status()
1002 	info->ue_count = obj->err_data.ue_count;  in amdgpu_ras_query_error_status()
1003 	info->ce_count = obj->err_data.ce_count;  in amdgpu_ras_query_error_status()
1006 		if (adev->smuio.funcs &&  in amdgpu_ras_query_error_status()
1007 		    adev->smuio.funcs->get_socket_id &&  in amdgpu_ras_query_error_status()
1008 		    adev->smuio.funcs->get_die_id) {  in amdgpu_ras_query_error_status()
1009 			dev_info(adev->dev, "socket: %d, die: %d "  in amdgpu_ras_query_error_status()
1013 					adev->smuio.funcs->get_socket_id(adev),  in amdgpu_ras_query_error_status()
1014 					adev->smuio.funcs->get_die_id(adev),  in amdgpu_ras_query_error_status()
1015 					obj->err_data.ce_count,  in amdgpu_ras_query_error_status()
1016 					get_ras_block_str(&info->head));  in amdgpu_ras_query_error_status()
1018 			dev_info(adev->dev, "%ld correctable hardware errors "  in amdgpu_ras_query_error_status()
1021 					obj->err_data.ce_count,  in amdgpu_ras_query_error_status()
1022 					get_ras_block_str(&info->head));  in amdgpu_ras_query_error_status()
1026 		if (adev->smuio.funcs &&  in amdgpu_ras_query_error_status()
1027 		    adev->smuio.funcs->get_socket_id &&  in amdgpu_ras_query_error_status()
1028 		    adev->smuio.funcs->get_die_id) {  in amdgpu_ras_query_error_status()
1029 			dev_info(adev->dev, "socket: %d, die: %d "  in amdgpu_ras_query_error_status()
1032 					adev->smuio.funcs->get_socket_id(adev),  in amdgpu_ras_query_error_status()
1033 					adev->smuio.funcs->get_die_id(adev),  in amdgpu_ras_query_error_status()
1034 					obj->err_data.ue_count,  in amdgpu_ras_query_error_status()
1035 					get_ras_block_str(&info->head));  in amdgpu_ras_query_error_status()
1037 			dev_info(adev->dev, "%ld uncorrectable hardware errors "  in amdgpu_ras_query_error_status()
1039 					obj->err_data.ue_count,  in amdgpu_ras_query_error_status()
1040 					get_ras_block_str(&info->head));  in amdgpu_ras_query_error_status()
1053 		return -EINVAL;  in amdgpu_ras_reset_error_status()
1055 	if (!block_obj || !block_obj->hw_ops)   {  in amdgpu_ras_reset_error_status()
1056 		dev_dbg_once(adev->dev, "%s doesn't config RAS function\n",  in amdgpu_ras_reset_error_status()
1058 		return -EINVAL;  in amdgpu_ras_reset_error_status()
1061 	if (block_obj->hw_ops->reset_ras_error_count)  in amdgpu_ras_reset_error_status()
1062 		block_obj->hw_ops->reset_ras_error_count(adev);  in amdgpu_ras_reset_error_status()
1066 		if (block_obj->hw_ops->reset_ras_error_status)  in amdgpu_ras_reset_error_status()
1067 			block_obj->hw_ops->reset_ras_error_status(adev);  in amdgpu_ras_reset_error_status()
1077 	struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);  in amdgpu_ras_error_inject()
1079 		.block_id =  amdgpu_ras_block_to_ta(info->head.block),  in amdgpu_ras_error_inject()
1080 		.inject_error_type = amdgpu_ras_error_to_ta(info->head.type),  in amdgpu_ras_error_inject()
1081 		.sub_block_index = info->head.sub_block_index,  in amdgpu_ras_error_inject()
1082 		.address = info->address,  in amdgpu_ras_error_inject()
1083 		.value = info->value,  in amdgpu_ras_error_inject()
1085 	int ret = -EINVAL;  in amdgpu_ras_error_inject()
1087 							info->head.block,  in amdgpu_ras_error_inject()
1088 							info->head.sub_block_index);  in amdgpu_ras_error_inject()
1091 		return -EINVAL;  in amdgpu_ras_error_inject()
1093 	if (!block_obj || !block_obj->hw_ops)	{  in amdgpu_ras_error_inject()
1094 		dev_dbg_once(adev->dev, "%s doesn't config RAS function\n",  in amdgpu_ras_error_inject()
1095 			     get_ras_block_str(&info->head));  in amdgpu_ras_error_inject()
1096 		return -EINVAL;  in amdgpu_ras_error_inject()
1100 	if (adev->gmc.xgmi.num_physical_nodes > 1) {  in amdgpu_ras_error_inject()
1106 	if (info->head.block == AMDGPU_RAS_BLOCK__GFX) {  in amdgpu_ras_error_inject()
1107 		if (block_obj->hw_ops->ras_error_inject)  in amdgpu_ras_error_inject()
1108 			ret = block_obj->hw_ops->ras_error_inject(adev, info);  in amdgpu_ras_error_inject()
1111 		if (block_obj->hw_ops->ras_error_inject)  in amdgpu_ras_error_inject()
1112 			ret = block_obj->hw_ops->ras_error_inject(adev, &block_info);  in amdgpu_ras_error_inject()
1114 			ret = psp_ras_trigger_error(&adev->psp, &block_info);  in amdgpu_ras_error_inject()
1118 		dev_err(adev->dev, "ras inject %s failed %d\n",  in amdgpu_ras_error_inject()
1119 			get_ras_block_str(&info->head), ret);  in amdgpu_ras_error_inject()
1125  * amdgpu_ras_query_error_count -- Get error counts of all IPs
1133  * supports RAS. Return -EOPNOTSUPP if the device doesn't support RAS.
1143 	if (!adev->ras_enabled || !con)  in amdgpu_ras_query_error_count()
1144 		return -EOPNOTSUPP;  in amdgpu_ras_query_error_count()
1153 	list_for_each_entry(obj, &con->head, node) {  in amdgpu_ras_query_error_count()
1155 			.head = obj->head,  in amdgpu_ras_query_error_count()
1163 		if (adev->ip_versions[MP0_HWIP][0] != IP_VERSION(11, 0, 2) &&  in amdgpu_ras_query_error_count()
1164 		    adev->ip_versions[MP0_HWIP][0] != IP_VERSION(11, 0, 4)) {  in amdgpu_ras_query_error_count()
1166 				dev_warn(adev->dev, "Failed to reset error counter and error status");  in amdgpu_ras_query_error_count()
1225  * .. code-block:: bash
1238 	struct amdgpu_device *adev = con->adev;  in amdgpu_ras_sysfs_badpages_read()
1240 		sizeof("0xabcdabcd : 0x12345678 : R\n") - 1;  in amdgpu_ras_sysfs_badpages_read()
1241 	unsigned int start = div64_ul(ppos + element_size - 1, element_size);  in amdgpu_ras_sysfs_badpages_read()
1242 	unsigned int end = div64_ul(ppos + count - 1, element_size);  in amdgpu_ras_sysfs_badpages_read()
1270 	return scnprintf(buf, PAGE_SIZE, "feature mask: 0x%x\n", con->features);  in amdgpu_ras_sysfs_features_read()
1277 	sysfs_remove_file_from_group(&adev->dev->kobj,  in amdgpu_ras_sysfs_remove_bad_page_node()
1278 				&con->badpages_attr.attr,  in amdgpu_ras_sysfs_remove_bad_page_node()
1286 		&con->features_attr.attr,  in amdgpu_ras_sysfs_remove_feature_node()
1294 	sysfs_remove_group(&adev->dev->kobj, &group);  in amdgpu_ras_sysfs_remove_feature_node()
1304 	if (!obj || obj->attr_inuse)  in amdgpu_ras_sysfs_create()
1305 		return -EINVAL;  in amdgpu_ras_sysfs_create()
1309 	snprintf(obj->fs_data.sysfs_name, sizeof(obj->fs_data.sysfs_name),  in amdgpu_ras_sysfs_create()
1310 		"%s_err_count", head->name);  in amdgpu_ras_sysfs_create()
1312 	obj->sysfs_attr = (struct device_attribute){  in amdgpu_ras_sysfs_create()
1314 			.name = obj->fs_data.sysfs_name,  in amdgpu_ras_sysfs_create()
1319 	sysfs_attr_init(&obj->sysfs_attr.attr);  in amdgpu_ras_sysfs_create()
1321 	if (sysfs_add_file_to_group(&adev->dev->kobj,  in amdgpu_ras_sysfs_create()
1322 				&obj->sysfs_attr.attr,  in amdgpu_ras_sysfs_create()
1325 		return -EINVAL;  in amdgpu_ras_sysfs_create()
1328 	obj->attr_inuse = 1;  in amdgpu_ras_sysfs_create()
1338 	if (!obj || !obj->attr_inuse)  in amdgpu_ras_sysfs_remove()
1339 		return -EINVAL;  in amdgpu_ras_sysfs_remove()
1341 	sysfs_remove_file_from_group(&adev->dev->kobj,  in amdgpu_ras_sysfs_remove()
1342 				&obj->sysfs_attr.attr,  in amdgpu_ras_sysfs_remove()
1344 	obj->attr_inuse = 0;  in amdgpu_ras_sysfs_remove()
1355 	list_for_each_entry_safe(obj, tmp, &con->head, node) {  in amdgpu_ras_sysfs_remove_all()
1356 		amdgpu_ras_sysfs_remove(adev, &obj->head);  in amdgpu_ras_sysfs_remove_all()
1381  * .. code-block:: bash
1390 	struct drm_minor  *minor = adev_to_drm(adev)->primary;  in amdgpu_ras_debugfs_create_ctrl_node()
1393 	dir = debugfs_create_dir(RAS_FS_NAME, minor->debugfs_root);  in amdgpu_ras_debugfs_create_ctrl_node()
1399 			   &con->bad_page_cnt_threshold);  in amdgpu_ras_debugfs_create_ctrl_node()
1400 	debugfs_create_x32("ras_hw_enabled", 0444, dir, &adev->ras_hw_enabled);  in amdgpu_ras_debugfs_create_ctrl_node()
1401 	debugfs_create_x32("ras_enabled", 0444, dir, &adev->ras_enabled);  in amdgpu_ras_debugfs_create_ctrl_node()
1404 	con->de_ras_eeprom_table = debugfs_create_file("ras_eeprom_table",  in amdgpu_ras_debugfs_create_ctrl_node()
1407 	amdgpu_ras_debugfs_set_ret_size(&con->eeprom_control);  in amdgpu_ras_debugfs_create_ctrl_node()
1417 	debugfs_create_bool("auto_reboot", S_IWUGO | S_IRUGO, dir, &con->reboot);  in amdgpu_ras_debugfs_create_ctrl_node()
1424 			    &con->disable_ras_err_cnt_harvest);  in amdgpu_ras_debugfs_create_ctrl_node()
1432 	struct ras_manager *obj = amdgpu_ras_find_obj(adev, &head->head);  in amdgpu_ras_debugfs_create()
1439 	memcpy(obj->fs_data.debugfs_name,  in amdgpu_ras_debugfs_create()
1440 			head->debugfs_name,  in amdgpu_ras_debugfs_create()
1441 			sizeof(obj->fs_data.debugfs_name));  in amdgpu_ras_debugfs_create()
1443 	debugfs_create_file(obj->fs_data.debugfs_name, S_IWUGO | S_IRUGO, dir,  in amdgpu_ras_debugfs_create()
1463 	list_for_each_entry(obj, &con->head, node) {  in amdgpu_ras_debugfs_create_all()
1464 		if (amdgpu_ras_is_supported(adev, obj->head.block) &&  in amdgpu_ras_debugfs_create_all()
1465 			(obj->attr_inuse == 1)) {  in amdgpu_ras_debugfs_create_all()
1467 					get_ras_block_str(&obj->head));  in amdgpu_ras_debugfs_create_all()
1468 			fs_info.head = obj->head;  in amdgpu_ras_debugfs_create_all()
1488 		&con->features_attr.attr,  in amdgpu_ras_fs_init()
1498 	con->features_attr = dev_attr_features;  in amdgpu_ras_fs_init()
1505 		con->badpages_attr = bin_attr_gpu_vram_bad_pages;  in amdgpu_ras_fs_init()
1506 		bin_attrs[0] = &con->badpages_attr;  in amdgpu_ras_fs_init()
1511 	r = sysfs_create_group(&adev->dev->kobj, &group);  in amdgpu_ras_fs_init()
1513 		dev_err(adev->dev, "Failed to create RAS sysfs group!");  in amdgpu_ras_fs_init()
1524 		list_for_each_entry_safe(con_obj, tmp, &con->head, node) {  in amdgpu_ras_fs_fini()
1525 			ip_obj = amdgpu_ras_find_obj(adev, &con_obj->head);  in amdgpu_ras_fs_fini()
1550 	if (adev->nbio.ras &&  in amdgpu_ras_interrupt_fatal_error_handler()
1551 	    adev->nbio.ras->handle_ras_controller_intr_no_bifring)  in amdgpu_ras_interrupt_fatal_error_handler()
1552 		adev->nbio.ras->handle_ras_controller_intr_no_bifring(adev);  in amdgpu_ras_interrupt_fatal_error_handler()
1554 	if (adev->nbio.ras &&  in amdgpu_ras_interrupt_fatal_error_handler()
1555 	    adev->nbio.ras->handle_ras_err_event_athub_intr_no_bifring)  in amdgpu_ras_interrupt_fatal_error_handler()
1556 		adev->nbio.ras->handle_ras_err_event_athub_intr_no_bifring(adev);  in amdgpu_ras_interrupt_fatal_error_handler()
1563 	struct amdgpu_device *adev = obj->adev;  in amdgpu_ras_interrupt_poison_consumption_handler()
1566 		amdgpu_ras_get_ras_block(adev, obj->head.block, 0);  in amdgpu_ras_interrupt_poison_consumption_handler()
1568 	if (!block_obj || !block_obj->hw_ops)  in amdgpu_ras_interrupt_poison_consumption_handler()
1575 	if (block_obj->hw_ops->query_poison_status) {  in amdgpu_ras_interrupt_poison_consumption_handler()
1576 		poison_stat = block_obj->hw_ops->query_poison_status(adev);  in amdgpu_ras_interrupt_poison_consumption_handler()
1579 			dev_info(adev->dev, "No RAS poison status in %s poison IH.\n",  in amdgpu_ras_interrupt_poison_consumption_handler()
1580 					block_obj->ras_comm.name);  in amdgpu_ras_interrupt_poison_consumption_handler()
1586 	if (!adev->gmc.xgmi.connected_to_cpu)  in amdgpu_ras_interrupt_poison_consumption_handler()
1589 	if (block_obj->hw_ops->handle_poison_consumption)  in amdgpu_ras_interrupt_poison_consumption_handler()
1590 		poison_stat = block_obj->hw_ops->handle_poison_consumption(adev);  in amdgpu_ras_interrupt_poison_consumption_handler()
1594 		dev_info(adev->dev, "GPU reset for %s RAS poison consumption is issued!\n",  in amdgpu_ras_interrupt_poison_consumption_handler()
1595 				block_obj->ras_comm.name);  in amdgpu_ras_interrupt_poison_consumption_handler()
1603 	dev_info(obj->adev->dev,  in amdgpu_ras_interrupt_poison_creation_handler()
1610 	struct ras_ih_data *data = &obj->ih_data;  in amdgpu_ras_interrupt_umc_handler()
1614 	if (!data->cb)  in amdgpu_ras_interrupt_umc_handler()
1620 	ret = data->cb(obj->adev, &err_data, entry);  in amdgpu_ras_interrupt_umc_handler()
1630 		obj->err_data.ue_count += err_data.ue_count;  in amdgpu_ras_interrupt_umc_handler()
1631 		obj->err_data.ce_count += err_data.ce_count;  in amdgpu_ras_interrupt_umc_handler()
1637 	struct ras_ih_data *data = &obj->ih_data;  in amdgpu_ras_interrupt_handler()
1640 	while (data->rptr != data->wptr) {  in amdgpu_ras_interrupt_handler()
1642 		memcpy(&entry, &data->ring[data->rptr],  in amdgpu_ras_interrupt_handler()
1643 				data->element_size);  in amdgpu_ras_interrupt_handler()
1646 		data->rptr = (data->aligned_element_size +  in amdgpu_ras_interrupt_handler()
1647 				data->rptr) % data->ring_size;  in amdgpu_ras_interrupt_handler()
1649 		if (amdgpu_ras_is_poison_mode_supported(obj->adev)) {  in amdgpu_ras_interrupt_handler()
1650 			if (obj->head.block == AMDGPU_RAS_BLOCK__UMC)  in amdgpu_ras_interrupt_handler()
1655 			if (obj->head.block == AMDGPU_RAS_BLOCK__UMC)  in amdgpu_ras_interrupt_handler()
1658 				dev_warn(obj->adev->dev,  in amdgpu_ras_interrupt_handler()
1659 					"No RAS interrupt handler for non-UMC block with poison disabled.\n");  in amdgpu_ras_interrupt_handler()
1677 	struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);  in amdgpu_ras_interrupt_dispatch()
1678 	struct ras_ih_data *data = &obj->ih_data;  in amdgpu_ras_interrupt_dispatch()
1681 		return -EINVAL;  in amdgpu_ras_interrupt_dispatch()
1683 	if (data->inuse == 0)  in amdgpu_ras_interrupt_dispatch()
1687 	memcpy(&data->ring[data->wptr], info->entry,  in amdgpu_ras_interrupt_dispatch()
1688 			data->element_size);  in amdgpu_ras_interrupt_dispatch()
1691 	data->wptr = (data->aligned_element_size +  in amdgpu_ras_interrupt_dispatch()
1692 			data->wptr) % data->ring_size;  in amdgpu_ras_interrupt_dispatch()
1694 	schedule_work(&data->ih_work);  in amdgpu_ras_interrupt_dispatch()
1706 		return -EINVAL;  in amdgpu_ras_interrupt_remove_handler()
1708 	data = &obj->ih_data;  in amdgpu_ras_interrupt_remove_handler()
1709 	if (data->inuse == 0)  in amdgpu_ras_interrupt_remove_handler()
1712 	cancel_work_sync(&data->ih_work);  in amdgpu_ras_interrupt_remove_handler()
1714 	kfree(data->ring);  in amdgpu_ras_interrupt_remove_handler()
1732 			return -EINVAL;  in amdgpu_ras_interrupt_add_handler()
1738 	data = &obj->ih_data;  in amdgpu_ras_interrupt_add_handler()
1742 		.cb = ras_obj->ras_cb,  in amdgpu_ras_interrupt_add_handler()
1748 	INIT_WORK(&data->ih_work, amdgpu_ras_interrupt_process_handler);  in amdgpu_ras_interrupt_add_handler()
1750 	data->aligned_element_size = ALIGN(data->element_size, 8);  in amdgpu_ras_interrupt_add_handler()
1752 	data->ring_size = 64 * data->aligned_element_size;  in amdgpu_ras_interrupt_add_handler()
1753 	data->ring = kmalloc(data->ring_size, GFP_KERNEL);  in amdgpu_ras_interrupt_add_handler()
1754 	if (!data->ring) {  in amdgpu_ras_interrupt_add_handler()
1756 		return -ENOMEM;  in amdgpu_ras_interrupt_add_handler()
1760 	data->inuse = 1;  in amdgpu_ras_interrupt_add_handler()
1770 	list_for_each_entry_safe(obj, tmp, &con->head, node) {  in amdgpu_ras_interrupt_remove_all()
1771 		amdgpu_ras_interrupt_remove_handler(adev, &obj->head);  in amdgpu_ras_interrupt_remove_all()
1784 	if (!adev->ras_enabled || !con)  in amdgpu_ras_log_on_err_counter()
1787 	list_for_each_entry(obj, &con->head, node) {  in amdgpu_ras_log_on_err_counter()
1789 			.head = obj->head,  in amdgpu_ras_log_on_err_counter()
1808 			(adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 2)))  in amdgpu_ras_log_on_err_counter()
1813 		if (adev->ip_versions[MP0_HWIP][0] != IP_VERSION(11, 0, 2) &&  in amdgpu_ras_log_on_err_counter()
1814 		    adev->ip_versions[MP0_HWIP][0] != IP_VERSION(11, 0, 4) &&  in amdgpu_ras_log_on_err_counter()
1815 		    adev->ip_versions[MP0_HWIP][0] != IP_VERSION(13, 0, 0)) {  in amdgpu_ras_log_on_err_counter()
1817 				dev_warn(adev->dev, "Failed to reset error counter and error status");  in amdgpu_ras_log_on_err_counter()
1831 	if ((info->head.block != AMDGPU_RAS_BLOCK__GFX) &&  in amdgpu_ras_error_status_query()
1832 		(info->head.block != AMDGPU_RAS_BLOCK__MMHUB))  in amdgpu_ras_error_status_query()
1836 					info->head.block,  in amdgpu_ras_error_status_query()
1837 					info->head.sub_block_index);  in amdgpu_ras_error_status_query()
1839 	if (!block_obj || !block_obj->hw_ops) {  in amdgpu_ras_error_status_query()
1840 		dev_dbg_once(adev->dev, "%s doesn't config RAS function\n",  in amdgpu_ras_error_status_query()
1841 			     get_ras_block_str(&info->head));  in amdgpu_ras_error_status_query()
1845 	if (block_obj->hw_ops->query_ras_error_status)  in amdgpu_ras_error_status_query()
1846 		block_obj->hw_ops->query_ras_error_status(adev);  in amdgpu_ras_error_status_query()
1855 	if (!adev->ras_enabled || !con)  in amdgpu_ras_query_err_status()
1858 	list_for_each_entry(obj, &con->head, node) {  in amdgpu_ras_query_err_status()
1860 			.head = obj->head,  in amdgpu_ras_query_err_status()
1880 	if (!con || !con->eh_data || !bps || !count)  in amdgpu_ras_badpages_read()
1881 		return -EINVAL;  in amdgpu_ras_badpages_read()
1883 	mutex_lock(&con->recovery_lock);  in amdgpu_ras_badpages_read()
1884 	data = con->eh_data;  in amdgpu_ras_badpages_read()
1885 	if (!data || data->count == 0) {  in amdgpu_ras_badpages_read()
1887 		ret = -EINVAL;  in amdgpu_ras_badpages_read()
1891 	*bps = kmalloc(sizeof(struct ras_badpage) * data->count, GFP_KERNEL);  in amdgpu_ras_badpages_read()
1893 		ret = -ENOMEM;  in amdgpu_ras_badpages_read()
1897 	for (; i < data->count; i++) {  in amdgpu_ras_badpages_read()
1899 			.bp = data->bps[i].retired_page,  in amdgpu_ras_badpages_read()
1903 		status = amdgpu_vram_mgr_query_page_status(&adev->mman.vram_mgr,  in amdgpu_ras_badpages_read()
1904 				data->bps[i].retired_page);  in amdgpu_ras_badpages_read()
1905 		if (status == -EBUSY)  in amdgpu_ras_badpages_read()
1907 		else if (status == -ENOENT)  in amdgpu_ras_badpages_read()
1911 	*count = data->count;  in amdgpu_ras_badpages_read()
1913 	mutex_unlock(&con->recovery_lock);  in amdgpu_ras_badpages_read()
1922 	struct amdgpu_device *adev = ras->adev;  in amdgpu_ras_do_recovery()
1925 	if (!ras->disable_ras_err_cnt_harvest) {  in amdgpu_ras_do_recovery()
1929 		if  (hive && adev->gmc.xgmi.num_physical_nodes > 1) {  in amdgpu_ras_do_recovery()
1930 			device_list_handle = &hive->device_list;  in amdgpu_ras_do_recovery()
1933 			list_add_tail(&adev->gmc.xgmi.head, &device_list);  in amdgpu_ras_do_recovery()
1946 	if (amdgpu_device_should_recover_gpu(ras->adev)) {  in amdgpu_ras_do_recovery()
1954 		amdgpu_device_gpu_recover(ras->adev, NULL, &reset_context);  in amdgpu_ras_do_recovery()
1956 	atomic_set(&ras->in_recovery, 0);  in amdgpu_ras_do_recovery()
1963 	unsigned int old_space = data->count + data->space_left;  in amdgpu_ras_realloc_eh_data_space()
1966 	void *bps = kmalloc(align_space * sizeof(*data->bps), GFP_KERNEL);  in amdgpu_ras_realloc_eh_data_space()
1969 		return -ENOMEM;  in amdgpu_ras_realloc_eh_data_space()
1972 	if (data->bps) {  in amdgpu_ras_realloc_eh_data_space()
1973 		memcpy(bps, data->bps,  in amdgpu_ras_realloc_eh_data_space()
1974 				data->count * sizeof(*data->bps));  in amdgpu_ras_realloc_eh_data_space()
1975 		kfree(data->bps);  in amdgpu_ras_realloc_eh_data_space()
1978 	data->bps = bps;  in amdgpu_ras_realloc_eh_data_space()
1979 	data->space_left += align_space - old_space;  in amdgpu_ras_realloc_eh_data_space()
1992 	if (!con || !con->eh_data || !bps || pages <= 0)  in amdgpu_ras_add_bad_pages()
1995 	mutex_lock(&con->recovery_lock);  in amdgpu_ras_add_bad_pages()
1996 	data = con->eh_data;  in amdgpu_ras_add_bad_pages()
2005 		if (!data->space_left &&  in amdgpu_ras_add_bad_pages()
2007 			ret = -ENOMEM;  in amdgpu_ras_add_bad_pages()
2011 		amdgpu_vram_mgr_reserve_range(&adev->mman.vram_mgr,  in amdgpu_ras_add_bad_pages()
2015 		memcpy(&data->bps[data->count], &bps[i], sizeof(*data->bps));  in amdgpu_ras_add_bad_pages()
2016 		data->count++;  in amdgpu_ras_add_bad_pages()
2017 		data->space_left--;  in amdgpu_ras_add_bad_pages()
2020 	mutex_unlock(&con->recovery_lock);  in amdgpu_ras_add_bad_pages()
2036 	if (!con || !con->eh_data)  in amdgpu_ras_save_bad_pages()
2039 	mutex_lock(&con->recovery_lock);  in amdgpu_ras_save_bad_pages()
2040 	control = &con->eeprom_control;  in amdgpu_ras_save_bad_pages()
2041 	data = con->eh_data;  in amdgpu_ras_save_bad_pages()
2042 	save_count = data->count - control->ras_num_recs;  in amdgpu_ras_save_bad_pages()
2043 	mutex_unlock(&con->recovery_lock);  in amdgpu_ras_save_bad_pages()
2047 					     &data->bps[control->ras_num_recs],  in amdgpu_ras_save_bad_pages()
2049 			dev_err(adev->dev, "Failed to save EEPROM table data!");  in amdgpu_ras_save_bad_pages()
2050 			return -EIO;  in amdgpu_ras_save_bad_pages()
2053 		dev_info(adev->dev, "Saved %d pages to EEPROM table.\n", save_count);  in amdgpu_ras_save_bad_pages()
2066 		&adev->psp.ras_context.ras->eeprom_control;  in amdgpu_ras_load_bad_pages()
2071 	if (control->ras_num_recs == 0 || amdgpu_bad_page_threshold == 0)  in amdgpu_ras_load_bad_pages()
2074 	bps = kcalloc(control->ras_num_recs, sizeof(*bps), GFP_KERNEL);  in amdgpu_ras_load_bad_pages()
2076 		return -ENOMEM;  in amdgpu_ras_load_bad_pages()
2078 	ret = amdgpu_ras_eeprom_read(control, bps, control->ras_num_recs);  in amdgpu_ras_load_bad_pages()
2080 		dev_err(adev->dev, "Failed to load EEPROM table records!");  in amdgpu_ras_load_bad_pages()
2082 		ret = amdgpu_ras_add_bad_pages(adev, bps, control->ras_num_recs);  in amdgpu_ras_load_bad_pages()
2091 	struct ras_err_handler_data *data = con->eh_data;  in amdgpu_ras_check_bad_page_unlock()
2095 	for (i = 0; i < data->count; i++)  in amdgpu_ras_check_bad_page_unlock()
2096 		if (addr == data->bps[i].retired_page)  in amdgpu_ras_check_bad_page_unlock()
2113 	if (!con || !con->eh_data)  in amdgpu_ras_check_bad_page()
2116 	mutex_lock(&con->recovery_lock);  in amdgpu_ras_check_bad_page()
2118 	mutex_unlock(&con->recovery_lock);  in amdgpu_ras_check_bad_page()
2128 	 * Justification of value bad_page_cnt_threshold in ras structure  in amdgpu_ras_validate_threshold()
2130 	 * Generally, -1 <= amdgpu_bad_page_threshold <= max record length  in amdgpu_ras_validate_threshold()
2134 	 *    - If amdgpu_bad_page_threshold = -1,  in amdgpu_ras_validate_threshold()
2137 	 *    - When the value from user is 0 < amdgpu_bad_page_threshold <  in amdgpu_ras_validate_threshold()
2141 	 *    - If amdgpu_bad_page_threshold = 0, bad page retirement  in amdgpu_ras_validate_threshold()
2147 		u64 val = adev->gmc.mc_vram_size;  in amdgpu_ras_validate_threshold()
2150 		con->bad_page_cnt_threshold = min(lower_32_bits(val),  in amdgpu_ras_validate_threshold()
2153 		con->bad_page_cnt_threshold = min_t(int, max_count,  in amdgpu_ras_validate_threshold()
2171 	 * adev->ras_enabled is unset, i.e. when "ras_enable"  in amdgpu_ras_recovery_init()
2174 	con->adev = adev;  in amdgpu_ras_recovery_init()
2176 	if (!adev->ras_enabled)  in amdgpu_ras_recovery_init()
2179 	data = &con->eh_data;  in amdgpu_ras_recovery_init()
2182 		ret = -ENOMEM;  in amdgpu_ras_recovery_init()
2186 	mutex_init(&con->recovery_lock);  in amdgpu_ras_recovery_init()
2187 	INIT_WORK(&con->recovery_work, amdgpu_ras_do_recovery);  in amdgpu_ras_recovery_init()
2188 	atomic_set(&con->in_recovery, 0);  in amdgpu_ras_recovery_init()
2189 	con->eeprom_control.bad_channel_bitmap = 0;  in amdgpu_ras_recovery_init()
2198 	if (adev->gmc.xgmi.pending_reset)  in amdgpu_ras_recovery_init()
2200 	ret = amdgpu_ras_eeprom_init(&con->eeprom_control, &exc_err_limit);  in amdgpu_ras_recovery_init()
2208 	if (con->eeprom_control.ras_num_recs) {  in amdgpu_ras_recovery_init()
2213 		amdgpu_dpm_send_hbm_bad_pages_num(adev, con->eeprom_control.ras_num_recs);  in amdgpu_ras_recovery_init()
2215 		if (con->update_channel_flag == true) {  in amdgpu_ras_recovery_init()
2216 			amdgpu_dpm_send_hbm_bad_channel_flag(adev, con->eeprom_control.bad_channel_bitmap);  in amdgpu_ras_recovery_init()
2217 			con->update_channel_flag = false;  in amdgpu_ras_recovery_init()
2222 	if ((adev->asic_type == CHIP_ALDEBARAN) &&  in amdgpu_ras_recovery_init()
2223 	    (adev->gmc.xgmi.connected_to_cpu))  in amdgpu_ras_recovery_init()
2229 	kfree((*data)->bps);  in amdgpu_ras_recovery_init()
2231 	con->eh_data = NULL;  in amdgpu_ras_recovery_init()
2233 	dev_warn(adev->dev, "Failed to initialize ras recovery! (%d)\n", ret);  in amdgpu_ras_recovery_init()
2242 		ret = -EINVAL;  in amdgpu_ras_recovery_init()
2250 	struct ras_err_handler_data *data = con->eh_data;  in amdgpu_ras_recovery_fini()
2256 	cancel_work_sync(&con->recovery_work);  in amdgpu_ras_recovery_fini()
2258 	mutex_lock(&con->recovery_lock);  in amdgpu_ras_recovery_fini()
2259 	con->eh_data = NULL;  in amdgpu_ras_recovery_fini()
2260 	kfree(data->bps);  in amdgpu_ras_recovery_fini()
2262 	mutex_unlock(&con->recovery_lock);  in amdgpu_ras_recovery_fini()
2271 		switch (adev->ip_versions[MP0_HWIP][0]) {  in amdgpu_ras_asic_supported()
2279 	if (adev->asic_type == CHIP_IP_DISCOVERY) {  in amdgpu_ras_asic_supported()
2280 		switch (adev->ip_versions[MP0_HWIP][0]) {  in amdgpu_ras_asic_supported()
2289 	return adev->asic_type == CHIP_VEGA10 ||  in amdgpu_ras_asic_supported()
2290 		adev->asic_type == CHIP_VEGA20 ||  in amdgpu_ras_asic_supported()
2291 		adev->asic_type == CHIP_ARCTURUS ||  in amdgpu_ras_asic_supported()
2292 		adev->asic_type == CHIP_ALDEBARAN ||  in amdgpu_ras_asic_supported()
2293 		adev->asic_type == CHIP_SIENNA_CICHLID;  in amdgpu_ras_asic_supported()
2303 	struct atom_context *ctx = adev->mode_info.atom_context;  in amdgpu_ras_get_quirks()
2308 	if (strnstr(ctx->vbios_version, "D16406",  in amdgpu_ras_get_quirks()
2309 		    sizeof(ctx->vbios_version)) ||  in amdgpu_ras_get_quirks()
2310 		strnstr(ctx->vbios_version, "D36002",  in amdgpu_ras_get_quirks()
2311 			sizeof(ctx->vbios_version)))  in amdgpu_ras_get_quirks()
2312 		adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__GFX);  in amdgpu_ras_get_quirks()
2326 	adev->ras_hw_enabled = adev->ras_enabled = 0;  in amdgpu_ras_check_supported()
2328 	if (!adev->is_atom_fw ||  in amdgpu_ras_check_supported()
2332 	if (!adev->gmc.xgmi.connected_to_cpu) {  in amdgpu_ras_check_supported()
2334 			dev_info(adev->dev, "MEM ECC is active.\n");  in amdgpu_ras_check_supported()
2335 			adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__UMC |  in amdgpu_ras_check_supported()
2338 			dev_info(adev->dev, "MEM ECC is not presented.\n");  in amdgpu_ras_check_supported()
2342 			dev_info(adev->dev, "SRAM ECC is active.\n");  in amdgpu_ras_check_supported()
2344 				adev->ras_hw_enabled |= ~(1 << AMDGPU_RAS_BLOCK__UMC |  in amdgpu_ras_check_supported()
2347 				if (adev->ip_versions[VCN_HWIP][0] == IP_VERSION(2, 6, 0))  in amdgpu_ras_check_supported()
2348 					adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__VCN |  in amdgpu_ras_check_supported()
2351 					adev->ras_hw_enabled &= ~(1 << AMDGPU_RAS_BLOCK__VCN |  in amdgpu_ras_check_supported()
2354 				adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__PCIE_BIF |  in amdgpu_ras_check_supported()
2359 			dev_info(adev->dev, "SRAM ECC is not presented.\n");  in amdgpu_ras_check_supported()
2364 		adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__GFX |  in amdgpu_ras_check_supported()
2372 	adev->ras_hw_enabled &= AMDGPU_RAS_BLOCK_MASK;  in amdgpu_ras_check_supported()
2374 	adev->ras_enabled = amdgpu_ras_enable == 0 ? 0 :  in amdgpu_ras_check_supported()
2375 		adev->ras_hw_enabled & amdgpu_ras_mask;  in amdgpu_ras_check_supported()
2382 	struct amdgpu_device *adev = con->adev;  in amdgpu_ras_counte_dw()
2387 	res = pm_runtime_get_sync(dev->dev);  in amdgpu_ras_counte_dw()
2394 		atomic_set(&con->ras_ce_count, ce_count);  in amdgpu_ras_counte_dw()
2395 		atomic_set(&con->ras_ue_count, ue_count);  in amdgpu_ras_counte_dw()
2398 	pm_runtime_mark_last_busy(dev->dev);  in amdgpu_ras_counte_dw()
2400 	pm_runtime_put_autosuspend(dev->dev);  in amdgpu_ras_counte_dw()
2417 		return -ENOMEM;  in amdgpu_ras_init()
2419 	con->adev = adev;  in amdgpu_ras_init()
2420 	INIT_DELAYED_WORK(&con->ras_counte_delay_work, amdgpu_ras_counte_dw);  in amdgpu_ras_init()
2421 	atomic_set(&con->ras_ce_count, 0);  in amdgpu_ras_init()
2422 	atomic_set(&con->ras_ue_count, 0);  in amdgpu_ras_init()
2424 	con->objs = (struct ras_manager *)(con + 1);  in amdgpu_ras_init()
2430 	if (!adev->ras_enabled || adev->asic_type == CHIP_VEGA10) {  in amdgpu_ras_init()
2434 		if (!adev->ras_enabled && adev->asic_type == CHIP_VEGA20) {  in amdgpu_ras_init()
2435 			con->features |= BIT(AMDGPU_RAS_BLOCK__GFX);  in amdgpu_ras_init()
2444 	con->update_channel_flag = false;  in amdgpu_ras_init()
2445 	con->features = 0;  in amdgpu_ras_init()
2446 	INIT_LIST_HEAD(&con->head);  in amdgpu_ras_init()
2448 	con->flags = RAS_DEFAULT_FLAGS;  in amdgpu_ras_init()
2453 	switch (adev->asic_type) {  in amdgpu_ras_init()
2457 		if (!adev->gmc.xgmi.connected_to_cpu) {  in amdgpu_ras_init()
2458 			adev->nbio.ras = &nbio_v7_4_ras;  in amdgpu_ras_init()
2459 			amdgpu_ras_register_ras_block(adev, &adev->nbio.ras->ras_block);  in amdgpu_ras_init()
2460 			adev->nbio.ras_if = &adev->nbio.ras->ras_block.ras_comm;  in amdgpu_ras_init()
2468 	if (adev->nbio.ras &&  in amdgpu_ras_init()
2469 	    adev->nbio.ras->init_ras_controller_interrupt) {  in amdgpu_ras_init()
2470 		r = adev->nbio.ras->init_ras_controller_interrupt(adev);  in amdgpu_ras_init()
2475 	if (adev->nbio.ras &&  in amdgpu_ras_init()
2476 	    adev->nbio.ras->init_ras_err_event_athub_interrupt) {  in amdgpu_ras_init()
2477 		r = adev->nbio.ras->init_ras_err_event_athub_interrupt(adev);  in amdgpu_ras_init()
2483 	if (adev->gmc.xgmi.connected_to_cpu) {  in amdgpu_ras_init()
2485 		con->poison_supported = true;  in amdgpu_ras_init()
2487 	else if (adev->df.funcs &&  in amdgpu_ras_init()
2488 	    adev->df.funcs->query_ras_poison_mode &&  in amdgpu_ras_init()
2489 	    adev->umc.ras &&  in amdgpu_ras_init()
2490 	    adev->umc.ras->query_ras_poison_mode) {  in amdgpu_ras_init()
2492 			adev->df.funcs->query_ras_poison_mode(adev);  in amdgpu_ras_init()
2494 			adev->umc.ras->query_ras_poison_mode(adev);  in amdgpu_ras_init()
2497 			con->poison_supported = true;  in amdgpu_ras_init()
2499 			dev_warn(adev->dev, "Poison setting is inconsistent in DF/UMC(%d:%d)!\n",  in amdgpu_ras_init()
2504 		r = -EINVAL;  in amdgpu_ras_init()
2508 	dev_info(adev->dev, "RAS INFO: ras initialized successfully, "  in amdgpu_ras_init()
2510 		 adev->ras_hw_enabled, adev->ras_enabled);  in amdgpu_ras_init()
2522 	if (adev->gmc.xgmi.connected_to_cpu)  in amdgpu_persistent_edc_harvesting_supported()
2540 	if (amdgpu_ras_reset_error_status(adev, ras_block->block) != 0)  in amdgpu_persistent_edc_harvesting()
2553        return con->poison_supported;  in amdgpu_ras_is_poison_mode_supported()
2566 	if (!amdgpu_ras_is_supported(adev, ras_block->block)) {  in amdgpu_ras_block_late_init()
2573 		if (adev->in_suspend || amdgpu_in_reset(adev)) {  in amdgpu_ras_block_late_init()
2585 	if (adev->in_suspend || amdgpu_in_reset(adev))  in amdgpu_ras_block_late_init()
2589 	if (ras_obj->ras_cb || (ras_obj->hw_ops &&  in amdgpu_ras_block_late_init()
2590 	    (ras_obj->hw_ops->query_poison_status ||  in amdgpu_ras_block_late_init()
2591 	    ras_obj->hw_ops->handle_poison_consumption))) {  in amdgpu_ras_block_late_init()
2604 		atomic_set(&con->ras_ce_count, ce_count);  in amdgpu_ras_block_late_init()
2605 		atomic_set(&con->ras_ue_count, ue_count);  in amdgpu_ras_block_late_init()
2611 	if (ras_obj->ras_cb)  in amdgpu_ras_block_late_init()
2635 	if (ras_obj->ras_cb)  in amdgpu_ras_block_late_fini()
2653 	if (!adev->ras_enabled || !con) {  in amdgpu_ras_resume()
2660 	if (con->flags & AMDGPU_RAS_FLAG_INIT_BY_VBIOS) {  in amdgpu_ras_resume()
2672 		list_for_each_entry_safe(obj, tmp, &con->head, node) {  in amdgpu_ras_resume()
2673 			if (!amdgpu_ras_is_supported(adev, obj->head.block)) {  in amdgpu_ras_resume()
2674 				amdgpu_ras_feature_enable(adev, &obj->head, 0);  in amdgpu_ras_resume()
2686 	if (!adev->ras_enabled || !con)  in amdgpu_ras_suspend()
2691 	if (con->features)  in amdgpu_ras_suspend()
2705 	list_for_each_entry_safe(node, tmp, &adev->ras_list, node) {  in amdgpu_ras_late_init()
2706 		if (!node->ras_obj) {  in amdgpu_ras_late_init()
2707 			dev_warn(adev->dev, "Warning: abnormal ras list node.\n");  in amdgpu_ras_late_init()
2711 		obj = node->ras_obj;  in amdgpu_ras_late_init()
2712 		if (obj->ras_late_init) {  in amdgpu_ras_late_init()
2713 			r = obj->ras_late_init(adev, &obj->ras_comm);  in amdgpu_ras_late_init()
2715 				dev_err(adev->dev, "%s failed to execute ras_late_init! ret:%d\n",  in amdgpu_ras_late_init()
2716 					obj->ras_comm.name, r);  in amdgpu_ras_late_init()
2720 			amdgpu_ras_block_late_init_default(adev, &obj->ras_comm);  in amdgpu_ras_late_init()
2731 	if (!adev->ras_enabled || !con)  in amdgpu_ras_pre_fini()
2736 	if (con->features)  in amdgpu_ras_pre_fini()
2748 	if (!adev->ras_enabled || !con)  in amdgpu_ras_fini()
2751 	list_for_each_entry_safe(ras_node, tmp, &adev->ras_list, node) {  in amdgpu_ras_fini()
2752 		if (ras_node->ras_obj) {  in amdgpu_ras_fini()
2753 			obj = ras_node->ras_obj;  in amdgpu_ras_fini()
2754 			if (amdgpu_ras_is_supported(adev, obj->ras_comm.block) &&  in amdgpu_ras_fini()
2755 			    obj->ras_fini)  in amdgpu_ras_fini()
2756 				obj->ras_fini(adev, &obj->ras_comm);  in amdgpu_ras_fini()
2758 				amdgpu_ras_block_late_fini_default(adev, &obj->ras_comm);  in amdgpu_ras_fini()
2762 		list_del(&ras_node->node);  in amdgpu_ras_fini()
2769 	WARN(con->features, "Feature mask is not cleared");  in amdgpu_ras_fini()
2771 	if (con->features)  in amdgpu_ras_fini()
2774 	cancel_delayed_work_sync(&con->ras_counte_delay_work);  in amdgpu_ras_fini()
2785 	if (!adev->ras_hw_enabled)  in amdgpu_ras_global_ras_isr()
2789 		dev_info(adev->dev, "uncorrectable hardware error"  in amdgpu_ras_global_ras_isr()
2798 	if (adev->asic_type == CHIP_VEGA20 &&  in amdgpu_ras_need_emergency_restart()
2799 	    adev->pm.fw_version <= 0x283400) {  in amdgpu_ras_need_emergency_restart()
2814 	if (!adev->ras_enabled && con->features & BIT(AMDGPU_RAS_BLOCK__GFX)) {  in amdgpu_release_ras_context()
2815 		con->features &= ~BIT(AMDGPU_RAS_BLOCK__GFX);  in amdgpu_release_ras_context()
2830 		if (adev && adev->gmc.xgmi.connected_to_cpu &&  in find_adev()
2831 		    adev->gmc.xgmi.physical_node_id == node_id)  in find_adev()
2858 	if (!m || !((smca_get_bank_type(m->extcpu, m->bank) == SMCA_UMC_V2) &&  in amdgpu_bad_page_notifier()
2859 		    (XEC(m->status, 0x3f) == 0x0)))  in amdgpu_bad_page_notifier()
2871 	gpu_id = GET_MCA_IPID_GPUID(m->ipid) - GPU_ID_OFFSET;  in amdgpu_bad_page_notifier()
2884 	umc_inst = GET_UMC_INST(m->ipid);  in amdgpu_bad_page_notifier()
2885 	ch_inst = GET_CHAN_INDEX(m->ipid);  in amdgpu_bad_page_notifier()
2887 	dev_info(adev->dev, "Uncorrectable error detected in UMC inst: %d, chan_idx: %d",  in amdgpu_bad_page_notifier()
2891 		kcalloc(adev->umc.max_ras_err_cnt_per_query,  in amdgpu_bad_page_notifier()
2894 		dev_warn(adev->dev,  in amdgpu_bad_page_notifier()
2902 	if (adev->umc.ras &&  in amdgpu_bad_page_notifier()
2903 	    adev->umc.ras->convert_ras_error_address)  in amdgpu_bad_page_notifier()
2904 		adev->umc.ras->convert_ras_error_address(adev,  in amdgpu_bad_page_notifier()
2905 			&err_data, m->addr, ch_inst, umc_inst);  in amdgpu_bad_page_notifier()
2950 	return adev->psp.ras_context.ras;  in amdgpu_ras_get_context()
2956 		return -EINVAL;  in amdgpu_ras_set_context()
2958 	adev->psp.ras_context.ras = ras_con;  in amdgpu_ras_set_context()
2970 	return ras && (adev->ras_enabled & (1 << block));  in amdgpu_ras_is_supported()
2977 	if (atomic_cmpxchg(&ras->in_recovery, 0, 1) == 0)  in amdgpu_ras_reset_gpu()
2978 		amdgpu_reset_domain_schedule(ras->adev->reset_domain, &ras->recovery_work);  in amdgpu_ras_reset_gpu()
2989 		return -EINVAL;  in amdgpu_ras_register_ras_block()
2996 		return -ENOMEM;  in amdgpu_ras_register_ras_block()
2998 	INIT_LIST_HEAD(&ras_node->node);  in amdgpu_ras_register_ras_block()
2999 	ras_node->ras_obj = ras_block_obj;  in amdgpu_ras_register_ras_block()
3000 	list_add_tail(&ras_node->node, &adev->ras_list);  in amdgpu_ras_register_ras_block()