250 	bp.resv = NULL;  in amdgpu_bo_create_reserved()
534 		.resv = bp->resv  in amdgpu_bo_create()
596 				 bp->resv, bp->destroy);  in amdgpu_bo_create()
612 		r = amdgpu_fill_buffer(bo, 0, bo->tbo.base.resv, &fence);  in amdgpu_bo_create()
616 		dma_resv_add_fence(bo->tbo.base.resv, fence,  in amdgpu_bo_create()
620 	if (!bp->resv)  in amdgpu_bo_create()
633 	if (!bp->resv)  in amdgpu_bo_create()
634 		dma_resv_unlock(bo->tbo.base.resv);  in amdgpu_bo_create()
767 	r = dma_resv_wait_timeout(bo->tbo.base.resv, DMA_RESV_USAGE_KERNEL,  in amdgpu_bo_kmap()
1130 	dma_resv_assert_held(bo->tbo.base.resv);  in amdgpu_bo_get_tiling_flags()
1311 			&& bo->base.resv != &bo->base._resv);  in amdgpu_bo_release_notify()
1312 	if (bo->base.resv == &bo->base._resv)  in amdgpu_bo_release_notify()
1320 	if (WARN_ON_ONCE(!dma_resv_trylock(bo->base.resv)))  in amdgpu_bo_release_notify()
1323 	r = amdgpu_fill_buffer(abo, AMDGPU_POISON, bo->base.resv, &fence);  in amdgpu_bo_release_notify()
1329 	dma_resv_unlock(bo->base.resv);  in amdgpu_bo_release_notify()
1401 	struct dma_resv *resv = bo->tbo.base.resv;  in amdgpu_bo_fence()  local
1404 	r = dma_resv_reserve_fences(resv, 1);  in amdgpu_bo_fence()
1411 	dma_resv_add_fence(resv, fence, shared ? DMA_RESV_USAGE_READ :  in amdgpu_bo_fence()
1429 int amdgpu_bo_sync_wait_resv(struct amdgpu_device *adev, struct dma_resv *resv,  in amdgpu_bo_sync_wait_resv()  argument
1437 	amdgpu_sync_resv(adev, &sync, resv, sync_mode, owner);  in amdgpu_bo_sync_wait_resv()
1457 	return amdgpu_bo_sync_wait_resv(adev, bo->tbo.base.resv,  in amdgpu_bo_sync_wait()
1474 	WARN_ON_ONCE(!dma_resv_is_locked(bo->tbo.base.resv) &&  in amdgpu_bo_gpu_offset()