Lines Matching defs:amdgpu_mes
63 struct amdgpu_mes { struct
64 struct amdgpu_device *adev;
66 struct mutex mutex_hidden;
68 struct idr pasid_idr;
69 struct idr gang_id_idr;
70 struct idr queue_id_idr;
71 struct ida doorbell_ida;
73 spinlock_t queue_id_lock;
75 uint32_t sched_version;
76 uint32_t kiq_version;
78 uint32_t total_max_queue;
79 uint32_t doorbell_id_offset;
80 uint32_t max_doorbell_slices;
82 uint64_t default_process_quantum;
83 uint64_t default_gang_quantum;
85 struct amdgpu_ring ring;
86 spinlock_t ring_lock;
88 const struct firmware *fw[AMDGPU_MAX_MES_PIPES];
91 struct amdgpu_bo *ucode_fw_obj[AMDGPU_MAX_MES_PIPES];
92 uint64_t ucode_fw_gpu_addr[AMDGPU_MAX_MES_PIPES];
93 uint32_t *ucode_fw_ptr[AMDGPU_MAX_MES_PIPES];
94 uint32_t ucode_fw_version[AMDGPU_MAX_MES_PIPES];
95 uint64_t uc_start_addr[AMDGPU_MAX_MES_PIPES];
98 struct amdgpu_bo *data_fw_obj[AMDGPU_MAX_MES_PIPES];
99 uint64_t data_fw_gpu_addr[AMDGPU_MAX_MES_PIPES];
100 uint32_t *data_fw_ptr[AMDGPU_MAX_MES_PIPES];
101 uint32_t data_fw_version[AMDGPU_MAX_MES_PIPES];
102 uint64_t data_start_addr[AMDGPU_MAX_MES_PIPES];
105 struct amdgpu_bo *eop_gpu_obj[AMDGPU_MAX_MES_PIPES];
106 uint64_t eop_gpu_addr[AMDGPU_MAX_MES_PIPES];
108 void *mqd_backup[AMDGPU_MAX_MES_PIPES];
109 struct amdgpu_irq_src irq[AMDGPU_MAX_MES_PIPES];
134 const struct amdgpu_mes_funcs *funcs; argument