827 	struct mes_misc_op_input op_input;  in amdgpu_mes_rreg()  local
830 	op_input.op = MES_MISC_OP_READ_REG;  in amdgpu_mes_rreg()
831 	op_input.read_reg.reg_offset = reg;  in amdgpu_mes_rreg()
832 	op_input.read_reg.buffer_addr = adev->mes.read_val_gpu_addr;  in amdgpu_mes_rreg()
839 	r = adev->mes.funcs->misc_op(&adev->mes, &op_input);  in amdgpu_mes_rreg()
852 	struct mes_misc_op_input op_input;  in amdgpu_mes_wreg()  local
855 	op_input.op = MES_MISC_OP_WRITE_REG;  in amdgpu_mes_wreg()
856 	op_input.write_reg.reg_offset = reg;  in amdgpu_mes_wreg()
857 	op_input.write_reg.reg_value = val;  in amdgpu_mes_wreg()
865 	r = adev->mes.funcs->misc_op(&adev->mes, &op_input);  in amdgpu_mes_wreg()
877 	struct mes_misc_op_input op_input;  in amdgpu_mes_reg_write_reg_wait()  local
880 	op_input.op = MES_MISC_OP_WRM_REG_WR_WAIT;  in amdgpu_mes_reg_write_reg_wait()
881 	op_input.wrm_reg.reg0 = reg0;  in amdgpu_mes_reg_write_reg_wait()
882 	op_input.wrm_reg.reg1 = reg1;  in amdgpu_mes_reg_write_reg_wait()
883 	op_input.wrm_reg.ref = ref;  in amdgpu_mes_reg_write_reg_wait()
884 	op_input.wrm_reg.mask = mask;  in amdgpu_mes_reg_write_reg_wait()
892 	r = adev->mes.funcs->misc_op(&adev->mes, &op_input);  in amdgpu_mes_reg_write_reg_wait()
903 	struct mes_misc_op_input op_input;  in amdgpu_mes_reg_wait()  local
906 	op_input.op = MES_MISC_OP_WRM_REG_WAIT;  in amdgpu_mes_reg_wait()
907 	op_input.wrm_reg.reg0 = reg;  in amdgpu_mes_reg_wait()
908 	op_input.wrm_reg.ref = val;  in amdgpu_mes_reg_wait()
909 	op_input.wrm_reg.mask = mask;  in amdgpu_mes_reg_wait()
917 	r = adev->mes.funcs->misc_op(&adev->mes, &op_input);  in amdgpu_mes_reg_wait()