Lines Matching refs:amdgpu_device

210 	void (*enable_watchdog_timer)(struct amdgpu_device *adev);
211 	bool (*query_utcl2_poison_status)(struct amdgpu_device *adev);
216 	uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev);
217 	void (*select_se_sh)(struct amdgpu_device *adev, u32 se_num,
219 	void (*read_wave_data)(struct amdgpu_device *adev, uint32_t simd,
221 	void (*read_wave_vgprs)(struct amdgpu_device *adev, uint32_t simd,
224 	void (*read_wave_sgprs)(struct amdgpu_device *adev, uint32_t simd,
227 	void (*select_me_pipe_q)(struct amdgpu_device *adev, u32 me, u32 pipe,
229 	void (*init_spm_golden)(struct amdgpu_device *adev);
230 	void (*update_perfmon_mgcg)(struct amdgpu_device *adev, bool enable);
378 int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev,
384 void amdgpu_gfx_kiq_fini(struct amdgpu_device *adev);
385 int amdgpu_gfx_kiq_init(struct amdgpu_device *adev,
388 int amdgpu_gfx_mqd_sw_init(struct amdgpu_device *adev,
390 void amdgpu_gfx_mqd_sw_fini(struct amdgpu_device *adev);
391 int amdgpu_gfx_disable_kcq(struct amdgpu_device *adev);
392 int amdgpu_gfx_enable_kcq(struct amdgpu_device *adev);
394 void amdgpu_gfx_compute_queue_acquire(struct amdgpu_device *adev);
395 void amdgpu_gfx_graphics_queue_acquire(struct amdgpu_device *adev);
397 int amdgpu_gfx_mec_queue_to_bit(struct amdgpu_device *adev, int mec,
399 void amdgpu_queue_mask_bit_to_mec_queue(struct amdgpu_device *adev, int bit,
401 bool amdgpu_gfx_is_mec_queue_enabled(struct amdgpu_device *adev, int mec,
403 bool amdgpu_gfx_is_high_priority_compute_queue(struct amdgpu_device *adev,
405 bool amdgpu_gfx_is_high_priority_graphics_queue(struct amdgpu_device *adev,
407 int amdgpu_gfx_me_queue_to_bit(struct amdgpu_device *adev, int me,
409 void amdgpu_gfx_bit_to_me_queue(struct amdgpu_device *adev, int bit,
411 bool amdgpu_gfx_is_me_queue_enabled(struct amdgpu_device *adev, int me,
413 void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool enable);
414 int amdgpu_get_gfx_off_status(struct amdgpu_device *adev, uint32_t *value);
415 int amdgpu_gfx_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block);
416 void amdgpu_gfx_ras_fini(struct amdgpu_device *adev);
417 int amdgpu_get_gfx_off_entrycount(struct amdgpu_device *adev, u64 *value);
418 int amdgpu_get_gfx_off_residency(struct amdgpu_device *adev, u32 *residency);
419 int amdgpu_set_gfx_off_residency(struct amdgpu_device *adev, bool value);
420 int amdgpu_gfx_process_ras_data_cb(struct amdgpu_device *adev,
423 int amdgpu_gfx_cp_ecc_error_irq(struct amdgpu_device *adev,
426 uint32_t amdgpu_kiq_rreg(struct amdgpu_device *adev, uint32_t reg);
427 void amdgpu_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v);
428 int amdgpu_gfx_get_num_kcq(struct amdgpu_device *adev);
429 void amdgpu_gfx_cp_init_microcode(struct amdgpu_device *adev, uint32_t ucode_id);