Lines Matching defs:amdgpu_gfx
272 struct amdgpu_gfx { struct
274 struct amdgpu_gfx_config config; argument
275 struct amdgpu_rlc rlc;
276 struct amdgpu_pfp pfp;
277 struct amdgpu_ce ce;
278 struct amdgpu_me me;
279 struct amdgpu_mec mec;
280 struct amdgpu_kiq kiq;
281 struct amdgpu_imu imu;
282 bool rs64_enable; /* firmware format */
283 const struct firmware *me_fw; /* ME firmware */
284 uint32_t me_fw_version;
285 const struct firmware *pfp_fw; /* PFP firmware */
286 uint32_t pfp_fw_version;
287 const struct firmware *ce_fw; /* CE firmware */
288 uint32_t ce_fw_version;
289 const struct firmware *rlc_fw; /* RLC firmware */
290 uint32_t rlc_fw_version;
291 const struct firmware *mec_fw; /* MEC firmware */
292 uint32_t mec_fw_version;
293 const struct firmware *mec2_fw; /* MEC2 firmware */
294 uint32_t mec2_fw_version;
295 const struct firmware *imu_fw; /* IMU firmware */
296 uint32_t imu_fw_version;
297 uint32_t me_feature_version;
298 uint32_t ce_feature_version;
299 uint32_t pfp_feature_version;
300 uint32_t rlc_feature_version;
301 uint32_t rlc_srlc_fw_version;
302 uint32_t rlc_srlc_feature_version;
303 uint32_t rlc_srlg_fw_version;
304 uint32_t rlc_srlg_feature_version;
305 uint32_t rlc_srls_fw_version;
306 uint32_t rlc_srls_feature_version;
307 uint32_t rlcp_ucode_version;
308 uint32_t rlcp_ucode_feature_version;
332 const struct amdgpu_gfx_funcs *funcs; argument
352 struct amdgpu_gfx_ras *ras; argument
357 #define amdgpu_gfx_get_gpu_clock_counter(adev) (adev)->gfx.funcs->get_gpu_clock_counter((adev)) argument